Chapter 1: Introduction.Chapter 2: The first-order delta-sigma modulator.Chapter 3: The second-order delta-sigma modulator.Chapter 4: Higher-order delta-sigma modulation.Chapter 5: Bandpass and quadrature delta-sigma modulation.Chapter 6: Implementation considerations for [Delta][Sigma] ADCs.Chapter 7: Delta-sigma DACs.Chapter 8: High-level design and simulation.Chapter 9: Example modulator systems.Appendix A: Spectral estimation.Appendix B: The delta-sigma toolbox.Appendix C: Noise in switched-capacitor delta-sigma data converters.

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Understanding Delta-Sigma Data Converters

A highly stable triple-integration noise-shaping technology which permits greater accuracy for monolithic audio A/D converters is discussed. Based on this technology, a 16-bit 24-kHz bandwidth A-D converter LSI with digital filters was successfully fabricated in 2-/spl mu/m CMOS technology. An SNR (S/(N+THD)) of 91 dB and a total harmonic distortion (THD) of 0.002% at full-scale input were attained.

/pdf/a-16-bit-oversampling-a-to-d-conversion-technology-using-4nzmp67uvp.pdf

A 16-bit oversampling A-to-D conversion technology using triple-integration noise shaping

Recently, various multibit noise-shaping digital-to-analog converters (DACs) have been proposed that use digital signal processing techniques to cause the DAC noise arising from analog component mismatches to be spectrally shaped. Such DACs have the potential to significantly increase the present precision limits of /spl Delta//spl Sigma/ data converters by eliminating the need for one-bit quantization in delta-sigma modulators. This paper extends the practicality of the noise-shaping DAC approach by presenting a general noise-shaping DAC architecture along with two special-case configurations that achieve first- and second-order noise-shaping, respectively. The second-order DAC configuration, in particular, is the least complex of those currently known to the author. Additionally, the paper provides a rigorous explanation of the apparent paradox of how the DAC noise can be spectrally shaped even though the sources of the DAC noise-the errors introduced by the analog circuitry-are not known to the noise-shaping algorithm.

Spectral shaping of circuit errors in digital-to-analog converters

A topology for high-precision noise-shaping converters that can be integrated on a standard digital IC process is presented. This topology uses a multibit noise-shaping coder and a novel form of dynamic element matching to achieve high accuracy and long-term stability without requiring precision matching of components. A fourth-order noise-shaping D/A (digital-to-analog) conversion system using a 3-b quantizer and a dynamic element-matching internal D/A converter, fabricated in a standard double-metal 3- mu m CMOS process, achieved 16-bit dynamic range and a harmonic distortion below -90 dB. This multibit noise-shaping D/A conversion system achieved performance comparable to that of a 1-bit noise-shaping D/A conversion system that operated at nearly four times its clock rate. >

A noise-shaping coder topology for 15+ bit converters

A switch, switched architecture and process for transferring data through an FCAL switch is disclosed. The switch uses multiple switch control circuits each coupled to one FCAL network and all connected to a crossbar switch. The switch control circuits are coupled together by a protocol bus for coordination purposes. Local conversations can occur on each FCAL loop and crossing conversations through the switch can occur concurrently. The OPN primitive is used to establish the connection before any data is transferred thereby eliminating the need for buffer memory in the switch control circuits. The destination address of each OPN is used to address a lookup table in each switch control circuit to determine if the destination node is local. If not, the destination is looked up and a connection request made on the protocol bus. If the remote port is not busy, it sends a reply which causes both ports to establish a data path through the backplane crossbar switch.

Fibre channel arbitrated loop bufferless switch circuitry to increase bandwidth without significant increase in cost

An integrated communications system. Comprising a substrate having a receiver disposed on the substrate for converting a received signal to an IF signal. Coupled to a VGA for low voltage applications and coupled to the receiver for processing the IF signal. The VGA includes a bank pair having a first bank of differential pairs of transistors and a second bank of differential pairs of transistors. The bank pair is cross-coupled in parallel, the IF signal is applied to the bank pair decoupled from a control signal used to control transconductance output gain of the bank pair over a range of input voltages. A digital IF demodulator is disposed on the substrate and coupled to the VGA for low voltage applications, for converting the IF signal to a demodulated baseband signal. And a transmitter is disposed on the substrate operating in cooperation with the receiver to establish a two way communications path.

Variable gain amplifier for low voltage applications

In a known current source arrangement which generates a current whose temperature coefficient is only equal to zero at one specific temperature, steps are taken, in accordance with the invention, to render the generated current independent of the temperature over a wide temperature range by compensation of the disturbing factor in the relationship between the generated current and the temperature.

Current stabilizing arrangement

A current-distribution circuit (1) supplies a plurality of substantially equal currents (i 1 , i 2 , i 3 and i 4 ) to a permutation circuit (13), which transfers these currents to outputs (18, 19, 20 and 21) in accordance with a cyclic permutation. The currents in these outputs exhibit a ripple caused by the inequality of the currents (i 1 , i 2 , i 3 and i 4 ). A detection circuit (30) detects the ripple component of the currents (i 1 , i 2 , i 3 and i 4 ) and applies this ripple component to a associated control circuit of a block of control circuits (50). The relevant control circuit supplies a control current for correcting the relevant current (i 1 , i 2 , i 3 or i 4 ) in such way that the ripple component is substantially eliminated.

Precision current-source arrangement

The subject of the invention is a differential sampler circuit including a voltage/current converter (1) having two differential inputs (E1a, E1b) and two outputs (S1a, S1b). According to the invention, each of these outputs is linked via an input multiplexer module (2a) to two interposed track-and-hold modules (5a, 6a), in such a way that at any instant one of the track-and-hold modules (5a, 6a) operates in track mode whereas the other (6a, 5a) operates in hold mode. These two modules (5a, 6a) are linked to the output (S4a) of the sampler circuit via an output multiplexer module (7a). This structure makes it possible to double the sampling frequency without increasing the intrinsic speed of the circuit. Each track-and-hold module (5a, 6a) includes an input load (10a, 11a) linked in parallel with a capacitor (C18a, C19a), an output emitter-follower transistor (T20a, T21a), and a switching cell (5-6a). Thus, the high-frequency performance of the circuit is improved.

Rudy J. Van De Plassche

Papers

Variable gain amplifier for low voltage applications

Current stabilizing arrangement

Precision current-source arrangement

Differential sampler circuit

Bandpass Sigma Delta Modulators