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Ryan Gary Kim

Researcher at Colorado State University

Publications -  33
Citations -  528

Ryan Gary Kim is an academic researcher from Colorado State University. The author has contributed to research in topics: Design space exploration & Network on a chip. The author has an hindex of 11, co-authored 30 publications receiving 390 citations. Previous affiliations of Ryan Gary Kim include Washington State University & Carnegie Mellon University.

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Journal ArticleDOI

On-Chip Communication Network for Efficient Training of Deep Convolutional Networks on Heterogeneous Manycore Systems

TL;DR: In this paper, a hybrid Network-on-Chip (NoC) architecture was proposed for energy-efficient training of CNNs on heterogeneous manycore platforms. But, the NoC architecture is not suitable for large-scale CNN architectures.
Journal ArticleDOI

Imitation Learning for Dynamic VFI Control in Large-Scale Manycore Systems

TL;DR: This work proposes the first architecture-independent IL-based methodology for dynamic VFI (DVFI) control in manycore systems and demonstrates that IL is able to obtain higher quality policies than RL with significantly less computation time and hardware area overheads.
Journal ArticleDOI

On-Chip Communication Network for Efficient Training of Deep Convolutional Networks on Heterogeneous Manycore Systems

TL;DR: This paper designs a hybrid Network-on-Chip (NoC) architecture, which consists of both wireline and wireless links, to improve the performance of CPU-GPU based heterogeneous manycore platforms running the above-mentioned CNN training workloads and demonstrates that the proposed hybrid NoC for heterogeneity manycore architectures is capable of significantly accelerating training of CNNs while remaining energy-efficient.
Journal ArticleDOI

Wireless NoC and Dynamic VFI Codesign: Energy Efficiency Without Performance Penalty

TL;DR: This paper explores the emerging paradigm of wireless NoC (WiNoC) and demonstrates that by incorporating WiNoC, VFI, and dynamic V/F tuning in a synergistic manner, it can design energy-efficient multicore platforms without introducing noticeable performance penalty.
Proceedings ArticleDOI

Hybrid network-on-chip architectures for accelerating deep learning kernels on heterogeneous manycore platforms

TL;DR: The proposed hybrid NoC achieves 1.9× reduction in network latency and improves the network throughput by a factor of 2 with respect to a highly optimized mesh NoC, demonstrating the capability of the proposed hybrid and heterogeneous manycore architecture in accelerating deep learning kernels in an energy-efficient manner.