This article presents a review on the current status, challenges, and potential future development opportunities for HgCdTe infrared materials and detectortechnology. A brief history of HgCdTe infrared technology is firstly summarized and discussed, leading to the conclusion that HgCdTe-based infrared detectors will continue to be a core infrared technology with expanded capabilities in the future due to a unique combination of its favourable properties. Recent progress and the current status of HgCdTe infrared technology are reviewed, including material growth,device architecture, device processing, surface passivation, and focal plane array applications. The further development of infrared applications requires that future infrared detectors have the features of lower cost, smaller pixel size, larger array format size, higher operating temperature, and multi-band detection, which presents a number of serious challenges to current HgCdTe-based infrared technology. The primary challenges include well controlled p-type doping, lower cost, larger array format size, higher operating temperature, multi-band detection, and advanced plasma dry etching. Various new concepts and technologies are proposed and discussed that have the potential to overcome the existing primary challenges that are inhibiting the development of next generation HgCdTeinfrared detectortechnology.

Progress, challenges, and opportunities for HgCdTe infrared materials and detectors

Reliability and performance limitations in SiC power devices

Gallium nitride self-aligned MOSFETs were fabricated using low-pressure chemical vapor-deposited silicon dioxide as the gate dielectric and polysilicon as the gate material. Silicon was implanted into an unintentionally doped GaN layer using the polysilicon gate to define the source and drain regions, with implant activation at 1100/spl deg/C for 5 min in nitrogen. The GaN MOSFETs have a low gate leakage current of less than 50 pA for circular devices with W/L=800/128 /spl mu/m. Devices are normally off with a threshold voltage of +2.7 V and a field-effect mobility of 45 cm/sup 2//Vs at room temperature. The minimum on-resistance measured is 1.9 m/spl Omega//spl middot/cm/sup 2/ with a gate voltage of 34 V (W/L=800/2 /spl mu/m). High-voltage lateral devices had a breakdown voltage of 700 V with gate-drain spacing of 9 /spl mu/m (80 V//spl mu/m), showing the feasibility of self-aligned GaN MOSFETs for high-voltage integrated circuits.

High-voltage normally off GaN MOSFETs on sapphire substrates

This study investigates the effect of hydrogen incorporation on amorphous indium–gallium–zinc oxide thin-film transistors (a-IGZO TFTs). The threshold voltage ( V th ) and subthreshold swing ( SS ) of hydrogen-incorporated a-IGZO TFTs were improved, and the threshold voltage shift (Δ V th ) in hysteresis loop was also suppressed from 4 V to 2 V. The physical property and chemical composition of a-IGZO films were analyzed by X-ray diffraction and X-ray photoelectron spectroscopy, respectively. Experimental results show that the hydrogen-induced passivation of the interface trap states between active layer and dielectric is responsible for the improvement of SS and V th .

Hydrogen-induced improvements in electrical characteristics of a-IGZO thin-film transistors

https://iopscience.iop.org/article/10.35848/1882-0786/abc787/pdf

Defect engineering in SiC technology for high-voltage power devices

A two-zone, lateral RESURF field 6H-SiC MOSFET with breakdown voltage as high as 1300 V and specific on-resistance of 160 m/spl Omega//spl middot/cm/sup 2/ has been fabricated. These MOSFETs exhibit stable and reversible breakdown indicating avalanche breakdown in SiC that has not been reported in earlier lateral SiC MOSFETs.

1300-V 6H-SiC lateral MOSFETs with two RESURF zones

High-voltage lateral RESURF MOSFETs have been fabricated on 4H-SiC with both nitrogen and phosphorus as source/drain and RESURF region implants. Blocking voltages as high as 1200 V and specific on-resistances of 4 /spl Omega/ cm/sup 2/ have been obtained, with the high on-resistance attributed to poor inversion layer mobility. Phosphorus is most appropriate for the source/drain implants due to low sheet resistance and contact resistance with low temperature anneals. However, poor activation of low dose phosphorus implants at 1200/spl deg/C makes nitrogen the preferred choice for the RESURF region.

High-voltage lateral RESURF MOSFETs on 4H-SiC

High-voltage lateral RESURF metal oxide semiconductor field effect transistors (MOSFETs) in 4H-SiC have been experimentally demonstrated, that block 900 V with a specific on-resistance of 0.5 /spl Omega/-cm/sup 2/. The RESURF dose in 4H-SiC to maximize the avalanche breakdown voltage is almost an order of magnitude higher than that of silicon; however this high RESURF dose leads to oxide breakdown and reliability concerns in thin (100-200 nm) gate oxide devices due to high electric field (>3-4 MV/cm) in the oxide. Lighter RESURF doses and/or thicker gate oxides are required in SiC lateral MOSFETs to achieve highest breakdown voltage capability.

Improved high-voltage lateral RESURF MOSFETs in 4H-SiC

The first lateral two-zone reduced surface field MOSFETs in 4H-SiC with NO annealing are reported. Interface properties of 4H-SiC-SiO/sub 2/ are improved, with inversion layer field-effect mobility increased to 25 cm/sup 2//V/spl middot/s, five times higher than that of dry reoxidation process, and with channel resistance significantly reduced. Devices are normally off with low leakage current. Threshold voltage is around 3 V. Blocking voltage of 930 V and specific on-resistance of 170 m/spl Omega//spl middot/cm/sup 2/ were obtained. Large-area devices with multifinger geometry are also demonstrated with scaled-up current. The output characteristics exhibit excellent linear and saturation regions.

930-V 170-m/spl Omega//spl middot/cm/sup 2/ lateral two-zone RESURF MOSFETs in 4H-SiC with NO annealing

The first lateral two-zone reduced surface field MOSFETs in 4H-SiC with NO annealing are reported Interface properties of 4H-SiC-SiO are improved, with inversion layer field-effect mobility increased to 25 cm V s, five times higher than that of dry reoxidation process, and with channel resistance significantly reduced Devices are normally off with low leakage current Threshold voltage is around 3 V Blocking voltage of 930 V and specific on-resistance of 170 m cm were obtained Large-area devices with multifinger geometry are also demon- strated with scaled-up current The output characteristics exhibit excellent linear and saturation regions Index Terms—Field-effect mobility, field-effect transistors, in- terface, MOS, NO annealing

S. Banerjee

Papers

1300-V 6H-SiC lateral MOSFETs with two RESURF zones

High-voltage lateral RESURF MOSFETs on 4H-SiC

Improved high-voltage lateral RESURF MOSFETs in 4H-SiC

930-V 170-m/spl Omega//spl middot/cm/sup 2/ lateral two-zone RESURF MOSFETs in 4H-SiC with NO annealing

930, 170Ω.cm2 Lateral Two-Zone RESURF MOSFETs in 4H-SiC with NO Annealing