Random testing requires each test to be selected randomly regardless of the tests previously applied. This paper introduces the concept of antirandom testing where each test applied is chosen such that its total distance from all previous tests is maximum. This spans the test vector space to the maximum extent possible for a given number of vectors. An algorithm for generating antirandom tests is presented. Compared with traditional pseudorandom testing, antirandom testing is found to be very effective when a high-fault coverage needs to be achieved with a limited number of test vectors. The superiority of the new approach is even more significant for testing bridging faults.

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Antirandom testing: a distance-based approach

Polynomial selection for LFSR-based BIST schemes has been typically left out of the scope of active research in the recent works due to lack of analytical methods that address this issue. Usage of primitive polynomial with a small number of feedbacks is considered a classical rule of thumb that is usually implemented. Although being beneficial for very long test sequences, primitive polynomial cannot guarantee fast fault coverage growth, which is a critical issue in pseudo-random-pattern-generator-based embedded test approaches. Hence, selecting a good initial state would be the main instrument for getting the fast coverage gain. In this work, we propose a formal analytical method to calculate a customized polynomial and seed pair for each separate design/test case. This novel technique allows shortening BIST runtimes and increasing fault coverage by embedding given efficient test patterns into the LFSR sequence. Being used in mixed-mode BIST techniques, the method shows decreasing trend in test application time and/or necessary test pattern storage resources. Our comparison against primitive polynomial based sequences support these observations.

Calculation of LFSR Seed and Polynomial Pair for BIST Applications

This chapter further details the topic of embedded self-test directing the reader towards the aspects of embedded test generation and test sequence optimization. We will brief the basics of widely used pseudorandom test generators and consider different techniques targeting the optimization of fault coverage characteristics of generated sequences. We will make the main focus on one optimization technique that is applicable to reseeding-based test generators and that uses a test compaction methodology. The technique exploits a great similarity in the way the faults are covered by pseudorandom sequences and by patterns generated for sequential designs. Hence, the test compaction methodology previously developed for the latter problem can be successfully reused in embedded testing.

Sequential Test Set Compaction in LFSR Reseeding

A central problem in built-in self test (BIST) is how to efficiently generate a small set of test vectors that detect all targeted faults. We propose a novel solution that uses linear algebraic concepts to partition the vector space of tests into subspaces (clusters). A subspace is defined by a compact set of basis vectors. We give an algorithm to compute sets of basis vectors defining the clusters. We also describe a low-cost logic circuit based on Gray codes that reproduces the subspaces from these basis vectors. Experimental results are presented which show that this approach reduces on-chip hardware overhead and test application time, while also guaranteeing full fault coverage.

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On-Chip Test Generation Using Linear Subspaces

Digital cores that are currently incorporated into advanced Systems on Chip (SoC) frequently include Logic Built-In Self-Test (LBIST) modules with the Self-Test Using MISR/Parallel Shift Register Sequence Generator (STUMPS) architecture. Such a solution always comprises a Pseudo-Random Pattern Generator (PRPG), usually designed as a Linear Feedback Shift Register (LFSR) with a phase shifter attached to the register and arranged as a network of XOR gates. This study discloses an original and innovative structure of such a PRPG unit referred to as the DT-LFSR-TPG module that needs no phase shifter. The module is designed as a set of identical linear registers of the DT-LFSR type with the same primitive polynomial. Each register has a form of a ring made up exclusively of D and T flip-flops. This study is focused on the investigation of those parameters of DT-LFSR registers that are essential to use these registers as components of PRPG modules. The investigated parameters include phase shifts and the correlation between sequences of bits appearing at outputs of T flip-flops, implementation cost, and the maximum frequency of the register operation. It is demonstrated that PRPG modules of the DT-LFSR-TPG type enable much higher phase shifts and substantially higher operation frequencies as compared to competitive solutions. Such modules can also drive significantly more scan paths than other PRPGs described in reference studies and based on phase shifters. However, the cost of the foregoing advantages of DT-LFSR-TPG modules is the larger hardware overhead associated with the implementation of the solution proposed.

A New, Fast Pseudo-Random Pattern Generator for Advanced Logic Built-In Self-Test Structures

In this paper, we investigate the use of Galois LFSRs (GLFSRs) as test pattern generators in BIST schemes that employ multiple scan chains. Current schemes use LFSRs or cellular automata (CA) with additional phase shifters to provide guaranteed minimum phase shifts between successive scan chains and also impose an upper bound on the number of taps for the XOR gate of each phase shifter. We compare CA with phase shifters (CAPSs) and GLFSRs without phase shifters in terms of the minimum inter-channel separation that they achieve and the overall XOR cost for each construction. Experimental results for different degrees show that GLFSRs are preferable in both hardware cost and fault coverage

S. Chidambaram

Papers

Comparative study of CA with phase shifters and GLFSRs