Showing papers by "S. Di Carlo published in 2006"

ATPG for Dynamic Burn-In Test in Full-Scan Circuits

Abstract: Yield and reliability are two key factors affecting costs and profits in the semiconductor industry. Stress testing is a technique based on the application of higher than usual levels of stress to speed up the deterioration of electronic devices and increase yield and reliability. One of the standard industrial approaches for stress testing is high temperature burn-in. This work proposes a full-scan circuit ATPG for dynamic burn-in. The goal of the proposed ATPG approach is to generate test patterns able to force transitions into each node of a full scan circuit to guarantee a uniform distribution of the stress during the dynamic burn-in test

Single-Event Upset Analysis and Protection in High Speed Circuits

Abstract: The effect of Single-Event Transients (SETs) (at a combinational node of a design) on the system reliability is becoming a big concern for ICs manufactured using advanced technologies. An SET at a node of combinational part may cause a transient pulse at the input of a flip-flop and consequently is latched in the flip-flop and generates a soft-error. When an SET conjoined with a transition at a node along a critical path of the combinational part of a design, a transient delay fault may occur at the input of a flip-flop. On the other hand, increasing pipeline depth and using low power techniques such as multi-level power supply, and multi-threshold transistor convert almost all paths in a circuit to critical ones. Thus, studying the behavior of the SET in these kinds of circuits needs special attention. This paper studies the dynamic behavior of a circuit with massive critical paths in the presence of an SET. We also propose a novel flip-flop architecture to mitigate the effects of such SETs in combinational circuits. Furthermore, the proposed architecture can tolerant a Single Event Upset (SEU) caused by particle strike on the internal nodes of a flip-flop.

Automatic March Tests Generations for Static Linked Faults in SRAMs

Abstract: Static linked faults are considered an interesting class of memory faults. Their capability of influencing the behavior of other faults causes the hiding of the fault effect and makes test algorithm design a very complex task. A large number of March tests with different fault coverage have been published and some methodologies have been presented to automatically generate March tests. In this paper we present an approach to automatically generate March tests for static linked faults. The proposed approach generates better test algorithms then previous, by reducing the test length

Automatic March tests generation for multi-port SRAMs

Abstract: Testing of Multi-Port (MP) SRAMs requires special tests since the multiple and simultaneous access can sensitize faults that are different from the conventional single-port memory faults. In spite of their growing use, few works have been published on testing MP memories. In addition, most of the published work concentrated only on two ports memories (i.e., 2P memories). This paper presents a methodology to automatically generate march tests for MP memories. It is based on generations of single port memory march test firstly, then extending it to test a generic MP SRAMs. A set of experimental results shows the effectiveness of the proposed solution.

A Unique March Test Algorithm for the Wide Spread of Realistic Memory Faults in SRAMs

Abstract: Among the different types of algorithms proposed to test static random access memories (SRAMs), march tests have proven to be faster, simpler and regularly structured. A large number of march tests with different fault coverage have been published. Usually different march tests detect only a specific set of memory faults. The always growing memory production technology introduces new classes of fault, making a key hurdle the generation of new march tests. The aim of this paper is to target the whole set of realistic fault model and to provide a unique march test able to reduce the test complexity of 15.4% than state-of-the-art march algorithm

A 22n March Test for Realistic Static Linked Faults in SRAMs

Abstract: Linked Faults are considered an interesting class of memory faults. Their capability of influencing the behavior of other faults causes the hiding of the fault effect and makes test algorithm design a very complex task. Although several March Tests have been developed for the wide memory faults spread, a few of them are able to detect linked faults. In the present paper March AB, a March Test targeting the set of realistic memory linked fault is presented. Comparison results show that the proposed March Test provides the same fault coverage of already published algorithms but, it reduces the test complexity and therefore the test time. Moreover, a complete taxonomy of linked faults will be presented.

A tool for teaching memory testing based on BIST

Abstract: The paper presents a tool that explains and demonstrates the essentials of RAM testing and memory built-in self-test. It also generates the BIST structure for the given memory matrix together with a march test which is provided by the march test generator according to the defined list of faults. The developed system was implemented as a Java applet what means its good compatibility regarding different hardware and operating system platforms, its safety and accessibility while it is placed on Internet. The presented tool has been utilised as the educational instrument in laboratory works.