[서평]「Digital Video Processing」

We present a new design for a 1-b full adder featuring hybrid-CMOS design style. The quest to achieve a good-drivability, noise-robustness, and low-energy operations for deep submicrometer guided our research to explore hybrid-CMOS style design. Hybrid-CMOS design style utilizes various CMOS logic style circuits to build new full adders with desired performance. This provides the designer a higher degree of design freedom to target a wide range of applications, thus significantly reducing design efforts. We also classify hybrid-CMOS full adders into three broad categories based upon their structure. Using this categorization, many full-adder designs can be conceived. We will present a new full-adder design belonging to one of the proposed categories. The new full adder is based on a novel xor-xnor circuit that generates xor and xnor full-swing outputs simultaneously. This circuit outperforms its counterparts showing 5%-37% improvement in the power-delay product (PDP). A novel hybrid-CMOS output stage that exploits the simultaneous xor-xnor signals is also proposed. This output stage provides good driving capability enabling cascading of adders without the need of buffer insertion between cascaded stages. There is approximately a 40% reduction in PDP when compared to its best counterpart. During our experimentations, we found out that many of the previously reported adders suffered from the problems of low swing and high noise when operated at low supply voltages. The proposed full adder is energy efficient and outperforms several standard full adders without trading off driving capability and reliability. The new full-adder circuit successfully operates at low voltages with excellent signal integrity and driving capability. To evaluate the performance of the new full adder in a real circuit, we embedded it in a 4- and 8-b, 4-operand carry-save array adder with final carry-propagate adder. The new adder displayed better performance as compared to the standard full adders

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Design of Robust, Energy-Efficient Full Adders for Deep-Submicrometer Design Using Hybrid-CMOS Logic Style

We present two high-speed and low-power full-adder cells designed with an alternative internal logic structure and pass-transistor logic styles that lead to have a reduced power-delay product (PDP). We carried out a comparison against other full-adders reported as having a low PDP, in terms of speed, power consumption and area. All the full-adders were designed with a 0.18-μm CMOS technology, and were tested using a comprehensive testbench that allowed to measure the current taken from the full-adder inputs, besides the current provided from the power-supply. Post-layout simulations show that the proposed full-adders outperform its counterparts exhibiting an average PDP advantage of 80%, with only 40% of relative area.

CMOS Full-Adders for Energy-Efficient Arithmetic Applications

In this paper, a hybrid 1-bit full adder design employing both complementary metal–oxide–semiconductor (CMOS) logic and transmission gate logic is reported. The design was first implemented for 1 bit and then extended for 32 bit also. The circuit was implemented using Cadence Virtuoso tools in 180-and 90-nm technology. Performance parameters such as power, delay, and layout area were compared with the existing designs such as complementary pass-transistor logic, transmission gate adder, transmission function adder, hybrid pass-logic with static CMOS output drive full adder, and so on. For 1.8-V supply at 180-nm technology, the average power consumption (4.1563 $\mu $ W) was found to be extremely low with moderately low delay (224 ps) resulting from the deliberate incorporation of very weak CMOS inverters coupled with strong transmission gates. Corresponding values of the same were 1.17664 $\mu $ W and 91.3 ps at 90-nm technology operating at 1.2-V supply voltage. The design was further extended for implementing 32-bit full adder also, and was found to be working efficiently with only 5.578-ns (2.45-ns) delay and 112.79- $\mu $ W (53.36- $\mu $ W) power at 180-nm (90-nm) technology for 1.8-V (1.2-V) supply voltage. In comparison with the existing full adder designs, the present implementation was found to offer significant improvement in terms of power and speed.

Performance Analysis of a Low-Power High-Speed Hybrid 1-bit Full Adder Circuit

Novel high-performance ternary circuits for nanotechnology are presented here. Each of these carbon nanotube field-effect transistor (CNFET)-based circuits implements all the possible kinds of ternary logic, including negative, positive and standard ternary logics, in one structure. The proposed designs have good driving capability and large noise margins and are robust. These circuits are designed based on the unique properties of CNFETs, such as the capability of setting the desired threshold voltage by changing the diameters of the nanotubes. This property of CNFETs makes them very suitable for the multiple- V t design method. The proposed circuits are simulated exhaustively, using Synopsys HSPICE with 32 nm-CNFET technology in various test situations and different supply voltages. Simulation results demonstrate great improvements in terms of speed, power consumption and insusceptibility to process variations with respect to other conventional and state-of-the-art 32 nm complementary metal-oxide semiconductor and CNFET-based ternary circuits. For instance at 0.9 V, the proposed ternary logic and arithmetic circuits consume on average 53 and 40 less energy, respectively, compared to the CNFET-based ternary logic and arithmetic circuits, recently proposed in the literature.

Design of energy-efficient and robust ternary circuits for nanotechnology

As we scale down to deep submicron (DSM) technology, noise is becoming a metric of equal importance as power, speed, and area. Smaller feature sizes, low voltage, and high frequency are some of the characteristics for DSM circuits. A novel design methodology for the design of energy-efficient noise-tolerant XOR-XNOR circuits that can operate at low voltages is proposed. The proposed circuits are characterized and compared with previously published circuits for reliability and energy efficiency. To test their driving capability, the proposed gates are implanted in an existing 5-2 compressor design and are shown to provide superior performance. The average noise threshold energy is used for quantifying the noise immunity. Simulation results show that the proposed circuits are more noise-immune and displays better power consumption results as well as power-delay product characteristics. Also, the circuits prove to be faster and successfully work at all ranges of supply voltage starting from 0.6 V to 3.3 V.

Novel design methodology for high-performance XOR-XNOR circuit design

We present a novel motion estimation engine (MEE) architecture that efficiently reuses search area data while fully utilizing the hardware resources. A 2-D processing element (PE) core is central to the architecture. Search area data flows both horizontally as well as vertically while the current block data is stationary. A clever PE design ensures simple but highly regular dataflow through the core avoiding long interconnect delays. For a search range of [?16,+15] and block size of 16, our architecture can perform motion estimation for 60 fps of 4CIF video at 100 Mhz.

An Efficient Data Reuse Motion Estimation Engine

Motion estimation (ME) process consumes up to 70% of the total encoding time of video transmission. Because it has a high coding efficiency and it is very scalable, the full search (FS) algorithm is considered to be the most popular ME algorithm. However, the main drawback of the FS algorithm is that it is computationally intensive. For this reason, FS is rarely used for real-time video coding. This paper proposes a simple and fast adaptive search window size (ASWS) algorithm that eliminates a significant amount of computations from the conventional FS algorithm. This is achieved by dynamically reducing the required search area for each reference block. Simulation results show that more than 94% of the candidate blocks are eliminated by our algorithm without significant loss in visual quality. This paper also presents an efficient and high-speed ME engine (MEE) architecture for the proposed ASWS algorithm. The MEE efficiently reuses the search area data to minimize the memory I/O while fully utilizing the available hardware resources. A smart processing element design along with an innovative data scheduling scheme allows the search area data to flow both horizontally and vertically, whereas the current block data remain stationary. This allows the proposed architecture a simple and highly regular dataflow through the core. Simulation results show that for a search range of [-16,+15] and a block size of 16×16, the proposed architecture performs the ME for 60 fps of 4CIF video at 100 MHz and easily outperforms many FS architectures.

High-speed Motion Estimation Architecture for Real-time Video Transmission

Block-based motion estimation algorithms are widely adopted by video coding standards due to their simplicity and good distortion performance. Amongst these, pattern based search algorithms are very popular. The basic assumption made by these algorithms is that there exists a unimodal error surface within the search window. As seen in real world video sequences, this is far from reality and the algorithms often get stuck in local minimums yielding sub-optimal results. We propose a multi-path search (MPS) algorithm that utilizes more than one path to find the absolute minima. Wrong search paths are avoided early resulting in faster search. Better motion vectors are estimated increasing the video quality, consequently reducing the bitrate requirement. MPS algorithm offers flexibility and robustness with better speed and quality. Results show that a speedup of upto 34% is achieved with slight increase in PSNR as compared to its best competitor. When compared to full search, the proposed algorithm looses only 0.1%~2% in PSNR while saving 92%~95% computations.

Multi-Path Search Algorithm for Block-Based Motion Estimation

Noise issues in deep submicron CMOS VLSI circuits have an importance comparable to area, delay and power consumption issues due to aggressive scaling trends in devices and interconnections. An attempt has been made to address this problem in this paper. A new technique to make dynamic CMOS circuits noise tolerant has been proposed by the authors. Simulation results for a dynamic-CMOS NAND gate and a dynamic-CMOS 1-bit full-adder circuit show that the proposed technique has an improvement in ANTE of 6.0X over conventional dynamic logic. The proposed technique, in comparison with the twin transistor technique, proves to improve ANTE by 2.8X. There is a large power dissipation incurred during the evaluation period for certain input combinations.

S. Goel

Papers

Novel design methodology for high-performance XOR-XNOR circuit design

An Efficient Data Reuse Motion Estimation Engine

High-speed Motion Estimation Architecture for Real-time Video Transmission

Multi-Path Search Algorithm for Block-Based Motion Estimation

A novel technique for noise-tolerance in dynamic circuits