We evaluate the impact of band-to-band tunneling (BTBT) on the characteristics of n-channel junctionless transistors (JLTs) A JLT that has a heavily doped channel, which is fully depleted in the off state, results in a significant band overlap between the channel and drain regions This overlap leads to a large BTBT of electrons from the channel to the drain in n-channel JLTs This BTBT leads to a nonnegligible increase in the off-state leakage current, which needs to be understood and alleviated In the case of n-channel JLTs, tunneling of electrons from the valence band of the channel to the conduction band of the drain leaves behind holes in the channel, which would raise the channel potential This triggers a parasitic bipolar junction transistor formed by the source, channel, and drain regions induced in a JLT in the off state Tunneling current is observed to be a strong function of the silicon body thickness and doping of a JLT We present guidelines to optimize the device for high on-to-off current ratio Finally, we compare the off-state leakage of bulk JLTs with that of silicon-on-insulator JLTs

Effect of Band-to-Band Tunneling on Junctionless Transistors

A drain current model available for full-range operation is derived for long-channel double-gate junctionless transistors. Including dopant and mobile carrier charges, a continuous 1-D charge model is derived by extending the concept of parabolic potential approximation for the subthreshold and the linear regions. Based on the continuous charge model, the Pao-Sah integral is analytically carried out to obtain a continuous drain current model. The proposed model is appropriate for compact modeling, because it continuously captures the phenomenon of the bulk conduction mechanism in all regions of device operation, including the subthreshold, linear, and saturation regions. It is shown that the model is in complete agreement with the numerical simulations for crucial device parameters and all operational voltage ranges.

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A Full-Range Drain Current Model for Double-Gate Junctionless Transistors

We propose the use of a high-κ spacer to improve the electrostatic integrity and, thereby, the scalability of silicon junctionless transistors (JLTs) for the first time. Using extensive simulations of n-channel JLTs, we demonstrate that the high-κ spacers improve the electrostatic integrity of JLTs at sub-22-nm gate lengths. Electric field that fringes through the high-κ spacer to the device layer on either sides of the gate results in an effective increase in electrical gate length in the off-state. However, the effective gate length is unaffected in the on-state. Hence, the off-state leakage current is reduced by several orders of magnitude with the use of a high-κ spacer with concomitent improvements in the subthreshold swing and drain-induced barrier lowering. A marginal improvement in the on-state current is observed with the use of the high-κ spacer, and this is related to the reduction in parasitic resistance in the silicon under the spacer due to fringe fields.

Enhanced Electrostatic Integrity of Short-Channel Junctionless Transistor With High- $\kappa$ Spacers

In this paper, we present a simulation study of analog circuit performance parameters for a symmetric double-gate junctionless transistor (DGJLT) using dual-material gate along with high- k spacer dielectric (DMG-SP) on both sides of the gate oxides of the device. The characteristics are demonstrated and compared with DMG DGJLT and single-material (conventional) gate (SMG) DGJLT. The DMG DGJLT presents superior transconductance (Gm), early voltage (VEA), and intrinsic gain (GmRO) compared with SMG DGJLT. The values are further improved for DMG-SP DGJLT, because high- k spacer enhances the fringing electric fields through the spacer.

A Dual-Material Gate Junctionless Transistor With High- $k$ Spacer for Enhanced Analog Performance

A silicon nanowire (Si-NW) with a gate-all-around (GAA) structure is implemented on a bulk wafer for a junctionless (JL) field-effect transistor (FET). A suspended Si-NW from the bulk-Si is realized using a deep reactive ion etching (RIE) process. The RIE process is iteratively applied to make multiply stacked Si-NWs, which can increase the on-state current when amplified with the number of iterations or enable integration of 3-D stacked Flash memory. The fabricated JL FETs exhibit excellent electrostatic control with the aid of the GAA and junction-free structure. The influence on device characteristics according to the channel dimensions and additional doping at the source and drain extension are studied for various geometric structures of the Si-NW.

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Investigation of Silicon Nanowire Gate-All-Around Junctionless Transistors Built on a Bulk Substrate

We propose a novel highly scalable source-drain-junction-free field-effect transistor that we call the bulk planar junctionless transistor (BPJLT). This builds upon the idea of an isolated ultrathin highly doped device layer of which volume is fully depleted in the off-state and is around flatband in the on-state. Here, the leakage current depends on the effective device layer thickness, and we show that with well doping and/or well bias, this can be controllably made less than the physical device layer thickness in a bulk planar junction-isolated structure. We demonstrate by extensive device simulations that these additional knobs for controlling short-channel effects reduce the off-state leakage current by orders of magnitude for similar on-state currents, making the BPJLT highly scalable.

S Gundapaneni

Papers

Bulk Planar Junctionless Transistor (BPJLT): An Attractive Device Alternative for Scaling