Showing papers in "IEEE Electron Device Letters in 2011"

1200-V Normally Off GaN-on-Si Field-Effect Transistors With Low Dynamic on -Resistance

Abstract: This letter reports high-voltage GaN field-effect transistors fabricated on Si substrates. A halide-based plasma treatment was performed to enable normally off operation. Atomic layer deposition of Al2O3 gate insulator was adopted to reduce the gate leakage current. Incorporation of multiple field plates, with one field plate connected to the gate electrode and two field plates connected to the source electrode successfully enabled a high breakdown voltage of 1200 V and low dynamic on-resistance at high-voltage operation.

Vertical Si-Nanowire $n$ -Type Tunneling FETs With Low Subthreshold Swing ( $\leq \hbox{50}\ \hbox{mV/decade}$ ) at Room Temperature

Abstract: This letter presents a Si nanowire based tunneling field-effect transistor (TFET) using a CMOS-compatible vertical gate-all-around structure. By minimizing the thermal budget with low-temperature dopant-segregated silicidation for the source-side dopant activation, excellent TFET characteristics were obtained. We have demonstrated for the first time the lowest ever reported subthreshold swing (SS) of 30 mV/decade at room temperature. In addition, we reported a very convincing SS of 50 mV/decade for close to three decades of drain current. Moreover, our TFET device exhibits excellent characteristics without ambipolar behavior and with high Ion/Ioff ratio (105), as well as low Drain-Induced Barrier Lowering of 70 mV/V.

Sensitivity of Threshold Voltage to Nanowire Width Variation in Junctionless Transistors

Abstract: We experimentally investigate the sensitivity of threshold voltage (T) to the variation of silicon nanowire (SiNW) width (Wsi) in gate-all-around junctionless transistors by comparison with inversion-mode transistors with the same geometric parameters. Due to the nature of junctionless transistors with a heavily doped SiNW channel, the VT fluctuation caused by the Wsi variation of junctionless transistors is significantly larger than that of inversion-mode transistors with a nearly intrinsic channel. This is because, in junctionless transistors, the channel doping concentration cannot be reduced in order to keep their inherent advantages. Therefore, our findings indicate that careful optimization or methods to mitigate the VT fluctuation related to the Wsi variation should be considered in junctionless transistors.

Comparison of Junctionless and Conventional Trigate Transistors With $L_{g}$ Down to 26 nm

Abstract: Junctionless accumulation-mode (JAM) devices with channel lengths Lg down to 26 nm were fabricated on a trigate process and compared to conventional inversion-mode (IM) devices. This letter represents the first experimental comparison of short-channel JAM-to-IM devices at matched off-state leakage (Ioff) . The JAM devices show better channel mobility (when moderately doped) and lower gate capacitance than the IM control counterparts at matched Ioff. However, the JAM devices also show reduced gate control and degraded short-channel characteristics. The observed degraded behavior of JAM relative to IM is explained with the aid of device simulations and a simple analytic model of the channel charge.

A Memristor Device Model

Abstract: This letter proposes a new mathematical model for memristor devices. It builds on existing models and is correlated against several published device characterizations. This letter identifies significant discrepancies between the existing models and published device characterization data. The proposed model addresses these discrepancies. In particular, it allows modeling of memristor-based neuromorphic systems.

Excellent Selector Characteristics of Nanoscale $ \hbox{VO}_{2}$ for High-Density Bipolar ReRAM Applications

Abstract: We herein present a nanoscale vanadium oxide (VO2) device with excellent selector characteristics such as a high on/off ratio (>; 50), fast switching speed ( ; 106 A/cm2). Owing to extrinsic defects, a large-area device with a 20-nm-thick VO2 layer underwent an electrical short. In contrast, after scaling the device active area (<; 5 × 104 nm2), excellent switching uniformity was obtained. This can be explained by the reduced defects and the metal-insulator transition of the whole nanoscale VO2. By integrating a bipolar resistive random access memory device with the VO2 selection device, a significantly improved readout margin was obtained. The VO2 selection device shows good potential for cross-point bipolar resistive memory applications.

300-GHz InAlN/GaN HEMTs With InGaN Back Barrier

Abstract: This letter reports lattice-matched In0.17Al0.83N/GaN high-electron-mobility transistors on a SiC substrate with a record current gain cutoff frequency (fT) of 300 GHz. To suppress the short-channel effects (SCEs), an In0.15Ga0.85N back barrier is applied in an InAlN/GaN heterostructure for the first time. The GaN channel thickness is also scaled to 26 nm, which allows a good immunity to SCEs for gate lengths down to 70 nm even with a relatively thick top barrier (9.4-10.4 nm). In a 30-nm-gate-length device with an on-resistance (Ron) of 1.2 Ω · mm and an extrinsic transconductance (gm.ext) of 530 mS/mm, a peak fa of 300 GHz is achieved. An electron velocity of 1.37-1.45 × 107 cm/s is extracted by two different delay analysis methods.

BN/Graphene/BN Transistors for RF Applications

Abstract: In this letter, we demonstrate the first BN/graphene/BN field-effect transistor for RF applications. This device structure can preserve the high mobility and the high carrier velocity of graphene, even when it is sandwiched between a substrate and a gate dielectric, and is hence very promising to enable the next generation of high-frequency graphene RF electronics.

Bulk Planar Junctionless Transistor (BPJLT): An Attractive Device Alternative for Scaling

Abstract: We propose a novel highly scalable source-drain-junction-free field-effect transistor that we call the bulk planar junctionless transistor (BPJLT). This builds upon the idea of an isolated ultrathin highly doped device layer of which volume is fully depleted in the off-state and is around flatband in the on-state. Here, the leakage current depends on the effective device layer thickness, and we show that with well doping and/or well bias, this can be controllably made less than the physical device layer thickness in a bulk planar junction-isolated structure. We demonstrate by extensive device simulations that these additional knobs for controlling short-channel effects reduce the off-state leakage current by orders of magnitude for similar on-state currents, making the BPJLT highly scalable.

Transparent Flexible Circuits Based on Amorphous-Indium–Gallium–Zinc–Oxide Thin-Film Transistors

Abstract: Circuits implemented with high-performance amorphous-indium-gallium-zinc-oxide thin-film transistors (TFTs) are realized on polyimide/polyethylene-terephthalate plastic substrates. The TFTs on plastic exhibit a saturation mobility of 19 cm2/V·s and a gate voltage swing of ~0.14 V/dec. For an input of 20 V, an 11-stage ring oscillator operates at 94.8 kHz with a propagation delay time of 0.48 μs. A shift register, consisting of ten TFTs and one capacitor, operates well with good bias stability. AC driving of pull-down TFTs gives the gate driver an improved lifetime of over ten years.

CMOS-Compatible Vertical-Silicon-Nanowire Gate-All-Around p-Type Tunneling FETs With $\leq 50$ -mV/decade Subthreshold Swing

Abstract: We present a vertical-silicon-nanowire-based p-type tunneling field-effect transistor (TFET) using CMOS-compatible process flow. Following our recently reported n-TFET , a low-temperature dopant segregation technique was employed on the source side to achieve steep dopant gradient, leading to excellent tunneling performance. The fabricated p-TFET devices demonstrate a subthreshold swing (SS) of 30 mV/decade averaged over a decade of drain current and an Ion/Ioff ratio of >; 105. Moreover, an SS of 50 mV/decade is maintained for three orders of drain current. This demonstration completes the complementary pair of TFETs to implement CMOS-like circuits.

Simple Analytical Bulk Current Model for Long-Channel Double-Gate Junctionless Transistors

Abstract: A bulk current model is formulated for long-channel double-gate junctionless (DGJL) transistors. Using a depletion approximation, an analytical expression is derived from the Poisson equation to find channel potential, which expresses the dependence of depletion width under an applied gate voltage. The depletion width equation is further simplified by the unique characteristic of junctionless transistors, i.e., a high channel doping concentration. From the depletion width formula, the bulk current model is constructed using Ohm's law. In addition, an analytical expression for subthreshold current is derived. The proposed model is compared with simulation data, revealing good agreement. The simplicity of the model gives a fast and easy way to understand, analyze, and design DGJL transistors comprehensively.

Proposal of a Spin Torque Majority Gate Logic

Abstract: A spin-based logic device is proposed. It is comprised of a common free ferromagnetic layer and four discrete ferromagnetic nanopillars, each containing an independent fixed layer. It has the functionality of a majority gate and is switched via motion of domain walls by spin transfer torque. Validity of its logic operation and a quantitative performance prediction are demonstrated by micromagnetic simulation. It is entirely compatible with complimentary metal-oxide-semiconductor technology.

Bipolar Nonlinear $\hbox{Ni/TiO}_{2}\hbox{/}\hbox{Ni}$ Selector for 1S1R Crossbar Array Applications

Abstract: A bipolar nonlinear selector to suppress the sneak current in the crossbar array has been fabricated using a simple Ni/TiO2/Ni metal-insulator-metal structure. The highly nonlinear current-voltage characteristics are realized by the Schottky emission over the Ni/TiO2 barriers. The series connection with an HfO2-resistive memory device shows reproducible bipolar resistive switching. The maximum array size with at least 10% read margin is projected to exceed megabits. This letter demonstrates the promise of the compact one selector-one resistor (1S1R) cell structure for high-density crossbar array applications.

Gate-All-Around Junctionless Transistors With Heavily Doped Polysilicon Nanowire Channels

Abstract: In this letter, we have investigated experimentally, for the first time, the feasibility of gate-all-around polycrystalline silicon (poly-Si) nanowire transistors with junctionless (JL) configuration by utilizing only one heavily doped poly-Si layer to serve as source, channel, and drain regions. In situ doped poly-Si material features high and uniform-doping concentration, facilitating the fabrication process. The developed JL device exhibits desirable electrostatic performance in terms of higher ON/OFF current ratio and lower source/drain series resistance as compared with the inversion-mode counterpart. Such scheme appears of great potential for future system-on-panel and 3-D IC applications.

$\hbox{HfO}_{x}/\hbox{TiO}_{x}/\hbox{HfO}_{x}/ \hbox{TiO}_{x}$ Multilayer-Based Forming-Free RRAM Devices With Excellent Uniformity

Abstract: In this letter, a significantly improved uniformity of device parameters (for cycle-to-cycle uniformity within one device and device-to-device uniformity), such as set voltage, reset voltage, and HRS and LRS resistance distributions, is successfully demonstrated on HfOx/TiOx multilayer (ML)-based resistive switching devices, as compared with HfOx-based single-layer device. In addition, the reported ML devices are free from forming process, which is greatly beneficial from the viewpoint of RRAM circuit operation. It is believed that both the Ti doping effect and the confinement of conduction filament within different dielectrics layers contribute to the improvement.

Impact of Graphene Interface Quality on Contact Resistance and RF Device Performance

Abstract: This letter demonstrates the importance of the graphene/metal interface on the ohmic contacts of high-frequency graphene transistors grown by chemical vapor deposition (CVD) on copper. Using an Al sacrificial layer during ohmic lithography, the graphene surface roughness underneath the ohmic contacts is reduced by fourfold, resulting in an improvement in the contact resistance from 2.0 to 0.2-0.5 kΩ·μm. Using this technology, top-gated CVD graphene transistors achieved direct-current transconductances of 200 mS/mm, maximum on current densities in excess of 1000 mA/mm, and hole mobilities ~ 1500-3000 cm2/(V·s) on silicon substrates. Radio-frequency device performance yielded an extrinsic current-gain cutoff frequency fT of 12 GHz after pad capacitance de-embedding resulting in an fT - LG product of 24 GHz·μm.

Self-Aligned Coplanar a-IGZO TFTs and Application to High-Speed Circuits

Abstract: We report a self-aligned coplanar amorphous indium-gallium-zinc-oxide (a-IGZO) thin-film transistor (TFT) using an a-IGZO/SiO2 stack layer. From the channel-length dependence of the total resistance for the TFTs, the channel and parasitic resistances were found to be 8.4 kΩ/μm and 9.7 kΩ/sq, respectively. The fabricated a-IGZO TFT exhibits field-effect mobility of 23.3 cm2/V ·s, threshold voltage of 3.6 V, and gate voltage swing of 203 mV/dec. A 23-stage ring oscillator made of the self-aligned TFTs exhibits a propagation delay time of 17 ns/stage at a supply voltage of 22 V.

A Distributed Model for Border Traps in $\hbox{Al}_{2} \hbox{O}_{3}-\hbox{InGaAs}$ MOS Devices

Abstract: A distributed border trap model based on tunneling between the semiconductor surface and trap states in the gate dielectric film is formulated to account for the observed frequency dispersion in the capacitance and conductance of Al2O3/InGaAs MOS devices biased in accumulation. The distributed circuit model is more physical and descriptive than previous lumped circuit border trap models in the literature. The distributed model correctly depicts the frequency dependence of both capacitance and conductance data in accumulation. A border trap volume density is extracted from the quantitative agreement with measured data.

Oxygen-Dependent Instability and Annealing/Passivation Effects in Amorphous In–Ga–Zn–O Thin-Film Transistors

Abstract: This letter discusses the reason for the instability of amorphous indium-gallium-zinc-oxide (a-IGZO) thin-film transistors (TFTs) under both positive and negative bias stresses. This instability is significantly influenced by the oxygen content in the bulk IGZO and the surrounding environment. The as-fabricated low-temperature devices can only endure a single polarized bias stress. An a-IGZO TFT that is stable toward both positive and negative bias stresses with large relaxation times of 95 × 104 and 371 × 104 s, respectively, is achieved by annealing and passivation.

All-Inkjet-Printed Organic Thin-Film Transistor Inverter on Flexible Plastic Substrate

Abstract: We report an all-inkjet-printed inverter using two p-type organic thin-film transistors (OTFTs) on a flexible plastic substrate. Metal-organic precursor-type silver ink, poly-4-vinylphenol solution, and 6,13-bis (triisopropylsilylethynyl)-pentacene solution were used to print gate and source/drain electrodes, gate-dielectric layer, and active semiconductor layer, respectively. By optimizing fabrication conditions, we obtained OTFTs with a mobility of 0.02 cm2/V·s, an on/off ratio of 104, and a threshold voltage of -1.2 V, and inverters with good switching performance showing a gain of 7.8 at a supply voltage of VDD = -40 V .

245-GHz InAlN/GaN HEMTs With Oxygen Plasma Treatment

Abstract: We report lattice-matched In0.17Al0.83N/GaN high-electron mobility transistors on a SiC substrate with a record current gain cutoff frequency (fT). The key to this performance is the use of an oxygen plasma treatment to form a thin oxide layer on the InAlN barrier and to reduce the gate leakage current by more than two orders of magnitude. In addition, the RF transconductance (gm) collapse is reduced in the O2-treated devices, which results in a significant improvement in the fT . In a transistor with a gate length of 30 nm, an fT of 245 GHz is achieved, the highest value ever reported in GaN-based field-effect transistors.

InAlN/GaN HEMTs With AlGaN Back Barriers

Abstract: This letter studies the effect of AlGaN back barriers in the dc and RF performance of In0.17Al0.83N/GaN high-electron mobility transistors grown on SiC substrates. When compared to conventional structures without a back barrier, the back barrier effectively prevents the degradation of drain-induced barrier lowering and significantly improves the output resistance in sub-100-nm-gate-length devices. The reduction in short-channel effects helps to increase the frequency performance of AlGaN back-barrier devices. For a 65-nm gate length, the current gain cutoff frequency (fT) of a transistor with an AlGaN back barrier is 210 GHz, which is higher than that of the standard device with the same gate length (fT = 195 GHz).

Enhanced Electrostatic Integrity of Short-Channel Junctionless Transistor With High- $\kappa$ Spacers

Abstract: We propose the use of a high-κ spacer to improve the electrostatic integrity and, thereby, the scalability of silicon junctionless transistors (JLTs) for the first time. Using extensive simulations of n-channel JLTs, we demonstrate that the high-κ spacers improve the electrostatic integrity of JLTs at sub-22-nm gate lengths. Electric field that fringes through the high-κ spacer to the device layer on either sides of the gate results in an effective increase in electrical gate length in the off-state. However, the effective gate length is unaffected in the on-state. Hence, the off-state leakage current is reduced by several orders of magnitude with the use of a high-κ spacer with concomitent improvements in the subthreshold swing and drain-induced barrier lowering. A marginal improvement in the on-state current is observed with the use of the high-κ spacer, and this is related to the reduction in parasitic resistance in the silicon under the spacer due to fringe fields.

Planar Nearly Ideal Edge-Termination Technique for GaN Devices

Abstract: In this letter, a simple edge termination is described which can be used to achieve nearly ideal parallel-plane breakdown voltage for GaN devices. This technique involves implanting a neutral species on the edges of devices to form a high-resistive amorphous layer. With this termination, formed by using argon implantation, the breakdown voltage of GaN Schottky barrier diodes was increased from 300 V for unterminated diodes to 1650 V after termination.

High-Performance Microwave Gate-Recessed AlGaN/AlN/GaN MOS-HEMT With 73% Power-Added Efficiency

Abstract: Gate-recessed AlGaN/AlN/GaN metal-oxide-semiconductor heterostructure high-mobility transistors (MOS-HEMTs) on SiC substrate are fabricated. The device with a gate length of 0.6 μm and a gate periphery of 100 μm exhibits a maximum dc drain current density of 1.59 A/mm at VGS = 3 V with an extrinsic transconductance (gm) of 374 mS/mm. An extrinsic current gain cutoff frequency (fT) of 19 GHz and a maximum oscillation frequency (fmax) of 50 GHz are deduced from S-parameter measurements. The output power density is 13 W/mm, and the associated power-added efficiency is 73% at 4-GHz frequency and 45-V drain bias. The power performance is comparable to state-of-the art AlGaN/GaN HEMTs, which demonstrates the great potential of gate-recessed MOS-HEMTs as a very promising alternative to GaN HEMTs.

AlGaN/GaN High-Electron-Mobility Transistors Fabricated Through a Au-Free Technology

Abstract: This letter reports undoped AlGaN/GaN high-electron-mobility transistors (HEMTs) fabricated with a Si-CMOS-compatible technology based on Ti/Al/W ohmic and Schottky contacts. The use of ohmic recess is key to reduce the contact resistance of this Au-free metallization below 0.5 Ω·mm. Comparison of HEMTs fabricated on the same wafer with and without ohmic recess shows that the recess provides a tenfold reduction in contact resistance, resulting in a fivefold lower forward voltage drop at IDS = 100 mA/mm. The reported Au-free AlGaN/GaN HEMT fabrication technology provides similar performance (i.e., contact resistance, leakage current, and breakdown voltage) than state-of-the-art Au-based AlGaN/GaN HEMTs and can be used in standard Si fabs without the risk of contamination.

Effects of TMAH Treatment on Device Performance of Normally Off $\hbox{Al}_{2}\hbox{O}_{3}/\hbox{GaN}$ MOSFET

Abstract: Normally off Al2O3/GaN MOSFETs are fabricated by utilizing a simple tetramethylammonium hydroxide (TMAH) treatment as a postgate-recess process. The TMAH-treated device with a gate length of 2.5 μm exhibited excellent device performances, such as a threshold voltage of 3.5 V, a maximum drain current of 336 mA/mm, and a breakdown voltage of 725 V, along with extremely small gate leakage current of about 10-9 A/mm at Vgs = 15 V, which is approximately six orders lower in magnitude compared to that of the device without TMAH treatment.

Buffer Thickness Contribution to Suppress Vertical Leakage Current With High Breakdown Field (2.3 MV/cm) for GaN on Si

Abstract: Vertical breakdown studies on AlGaN/GaN high-electron-mobility transistors (HEMTs) grown by metal-organic chemical vapor deposition (MOCVD) on a silicon substrate are studied to analyze the breakdown dependence with regard to i-GaN thickness (TGaN) and buffer thickness (TBuf). A high breakdown field (Ec) of 2.3 MV/cm was observed for MOCVD grown epilayers of total thickness of 5.5 μm on Si. Increasing TBuf is more significant than TGaN toward controlling the vertical leak age and demonstrates a high breakdown. For transistor operation at high voltages, GaN layers grown on thick buffers are highly resistive to the flow of leakage currents. A high figure of merit (BV2/Rd.ON) of 5.4 × 108 V2 · Ω-1· cm-2 was observed for an AlGaN/GaN HEMT grown on Si using a thick buffer.

Integrated Complementary Resistive Switches for Passive High-Density Nanocrossbar Arrays

Abstract: Recently, the sneak-path obstacle in passive crossbar arrays has been overcome by the invention of complementary resistive switches (CRSs) consisting of two bipolar antiserially connected memristive elements. Here, we demonstrate the vertical integration of CRS cells based on Cu/SiO2/Pt bipolar resistive switches. CRS cells were fabricated and electrically characterized, showing high resistance ratios (Roff/Ron >; 1500) and fast switching speed (<; 120 μs). The results are one step further toward the realization of high-density passive nanocrossbar-array-based gigabit memory devices.