Parameter variation in scaled technologies beyond 90nm will pose a major challenge for design of future high performance microprocessors. In this paper, we discuss process, voltage and temperature variations; and their impact on circuit and microarchitecture. Possible solutions to reduce the impact of parameter variations and to achieve higher frequency bins are also presented.

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Parameter variations and impact on circuits and microarchitecture

Bidirectional adaptive body bias (ABB) is used to compensate for die-to-die parameter variations by applying an optimum pMOS and nMOS body bias voltage to each die which maximizes the die frequency subject to a power constraint. Measurements on a 150 nm CMOS test chip which incorporates on-chip ABB, show that ABB reduces variation in die frequency by a factor of seven, while improving the die acceptance rate. An enhancement of this technique, that compensates for within-die parameter variations as well, increases the number of dies accepted in the highest frequency bin. ABB is therefore shown to provide bin split improvement in the presence of increasing process parameter variations.

Adaptive body bias for reducing impacts of die-to-die and within-die parameter variations on microprocessor frequency and leakage

Measurements on a 150 nm CMOS test chip show that on-chip bidirectional adaptive body biasing compensates effectively for die-to-die parameter variation to meet both frequency and leakage requirements. An enhancement of this technique to correct for within-die variations triples the accepted die count in the highest frequency bin.

Die-to-Die and Within-Die Parameter Variations on Microprocessor Frequency and Leakage

Dynamic voltage scaling (DVS) reduces the power consumption of processors when peak performance is unnecessary. However, the achievable power savings by DVS alone is becoming limited as leakage power increases. In this paper, we show how the simultaneous use of adaptive body biasing (ABB) and DVS can be used to reduce power in high-performance processors. Analytical models of the leakage current, dynamic power, and frequency as functions of supply voltage and body bias are derived and verified with SPICE simulation. We then show how to determine the correct trade-off between supply voltage and body bias for a given clock frequency and duration of operation. The usefulness of our approach is evaluated on real workloads obtained using real-time monitoring of processor utilization for four applications. The results demonstrate that application of simultaneous DVS and ABB results in an average energy reduction of 48% over DVS alone.

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Combined dynamic voltage scaling and adaptive body biasing for lower power microprocessors under dynamic workloads

In order to manage the active power consumption of high-performance digital designs, active leakage control techniques are required to provide significant leakage power savings coupled with fast time constants for entering and exiting idle mode. In this paper, dynamic sleep transistors and body bias are used in conjunction with clock gating to control active leakage for a 32-bit integer execution core in 130-nm CMOS technology. Measurements on pMOS sleep transistor reveal that lowest-leakage state is reached in less than 1 /spl mu/s, resulting in 37/spl times/ reduction in leakage power, while reactivation of block is achieved in less than two clock cycles. PMOS body bias reduces leakage power by 2/spl times/ with no performance penalty, and similar reactivation time. Power measurements at 4 GHz, 1.3 V, 75/spl deg/C demonstrate 8% total power reduction using dynamic body bias and 15% power reduction using a pMOS sleep transistor, for a typical activity profile.

Dynamic-sleep transistor and body bias for active leakage power control of microprocessors

Examines the effectiveness of opportunistic use of reverse body bias (RBB) to reduce leakage power during active operation, burn-in, and standby in 0.18 /spl mu/m single-V/sub t/ and 0.13 /spl mu/m dual-V/sub t/ logic process technologies. Investigates its dependencies on channel length, target V/sub t/, temperature and technology generation. Shows that RBB becomes less effective for leakage reduction at shorter channel lengths and lower V/sub t/ at both high and room temperatures, especially when target intrinsic leakage currents are high. RBB effectiveness also diminishes with technology scaling primarily because of worsening short-channel effects (SCE), particularly when target V/sub t/ values are low. A model is given that relates different transistor leakage components to full-chip leakage current, and is validated through test-chip measurements across a range of RBB values.

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S. Ma

Papers

Effectiveness of reverse body bias for leakage control in scaled dual Vt CMOS ICs