Wafer direct bonding refers to the process of adhesion of two flat mirror-polished wafers without using any intermediate gluing layers in ambient air or vacuum at room temperature. The adhesion of the two wafers occurs due to attractive long range van der Waals or hydrogen bonding forces. At room temperature the bonding energy of the interface is low and higher temperature annealing of the bonded wafer pairs has to be carried out to enhance the bonding energy. In this paper, we describe the prerequisites for the wafer-bonding process to occur and the methods to prepare the suitable surfaces for wafer bonding. The characterization techniques to assess the quality of the bonded interfaces and to measure the bonding energy are presented. Next, the applications of wafer direct bonding in the fabrication of novel engineered substrates such as "silicon-on-insulator" and other "on-insulator" substrates are detailed. These novel substrates, often called hybrid substrates, are fabricated using wafer bonding and layer splitting via a high dose hydrogen/helium implantation and subsequent annealing. The specifics of this process, also known as the smart-cut process, are introduced. Finally, the role of wafer bonding in future nanotechnology applications such as nanotransistor fabrication, three-dimensional integration for high-performance micro/nanoelectronics, nanotemplates based on twist bonding, and nano-electro-mechanical systems is discussed

Prolog to Wafer Direct Bonding: From Advance Substrate Engineering to Future Applications in Micro/Nanoelectronics

The feasibility of split capacitance-voltage (C-V) measurements in sub-0.1 /spl mu/m Si MOSFETs is demonstrated. Based on the split C-V measurements, an improved methodology to extract accurately the effective channel length and the effective mobility is proposed. Unlike conventional I/sub d/(V/sub g/)-based extraction techniques, this new approach does not assume the invariance of the effective mobility with gate length (assumption proved to be false in this paper). This method is relevant to study transport limitations in ultimate MOSFETs as illustrated with the study of pocket implant influence on 50-nm p-MOSFETs.

Improved split C-V method for effective mobility extraction in sub-0.1-/spl mu/m Si MOSFETs

A general ballistic FET model that was previously used for ballistic MOSFETs is applied to ballistic high electron mobility transistors (HEMTs), and the results are compared with experimental data for a sub-50 nm InAlAs-InGaAs HEMT. The results show that nanoscale HEMTs can be modeled as an intrinsic ballistic transistor with extrinsic source/drain series resistances. We also examine the "ballistic mobility" concept, a technique proposed for extending the drift-diffusion model to the quasi-ballistic regime. Comparison with a rigorous ballistic model shows that under low drain bias the ballistic mobility concept, although nonphysical, can be used to understand the experimental phenomena related to quasi-ballistic transport, such as the degradation of the apparent carrier mobility in short channel devices. We also point out that the ballistic mobility concept loses validity under high drain bias. The conclusions of this paper should be also applicable to other nanoscale transistors with high carrier mobility, such as carbon nanotube FETs and strained silicon MOSFETs.

Ballistic transport in high electron mobility transistors

With scaling of the gate length downward to increase speed and density, the gate dielectric thickness must also be reduced. However, this practice which has been in effect for many decades has reached a fundamental limitation because gate dielectric thicknesses in the range of tunneling have been reached with the SiO2 dielectric layer for MOSFETs. Consequently, the gate dielectrics with higher dielectric constants, dubbed the “high-κ”, which allow scaling with much larger thicknesses have become active research and development topics. In this review technological issues associated with the likely high-κ materials which are under consideration as well as challenges, and solution to them, they bring about in the fabrication of Si MOSFET are discussed. Moreover, in order to squeeze more speed out of CMOS, channels for both n- and p-type MOSFET enhanced with appropriate strain and the concepts behind them are discussed succinctly. Finally, the longer term approach of replacing Si with other channel materials such as GaAs (InGaAs) for n-channel and Ge for p-channel along with technological developments of their preparation on Si and likely gate oxide developments are treated in some detail.

High-κ dielectrics and advanced channel concepts for Si MOSFET

A method ( 100 ) of forming a transistor includes forming a gate structure ( 106, 108 ) over a semiconductor body and forming recesses ( 112 ) substantially aligned to the gate structure in the semiconductor body. Carbon-doped silicon is then epitaxially grown ( 114 ) in the recesses, followed by forming sidewall spacers ( 118 ) over lateral edges of the gate structure. The method continues by implanting source and drain regions in the semiconductor body ( 120 ) after forming the sidewall spacers. The carbon-doped silicon formed in the recesses resides close to the transistor channel and serves to provide a tensile stress to the channel, thereby facilitating improved carrier mobility in NMOS type transistor devices.

Transistor device containing carbon doped silicon in a recess next to MDD to create strain in channel

A novel mobility extraction technique showed that the mobility enhancements in strained Si MOSFETs were retained in deep sub-100 nm channel lengths. Mobility measurement in devices with channel lengths down to 40 nm was demonstrated by a dR/dL extraction method. The results confirmed and quantified the mobility enhancements despite the presence of high halo doping in scaled strained Si MOSFETs.

S. Narasimha

Papers

Low field mobility characteristics of sub-100 nm unstrained and strained Si MOSFETs