Disclosed is an improved approach for maintaining the structures for objects in a layout. A single type of structure is maintained that can be used to store or track a polygon of any shape, as long as the shape possesses a supported number of sides. The structure is capable of supporting irregular polygons or objects having angled edges. In one approach, the structure maintains information about each polygon as if that polygon is an octagon. Therefore, any polygon having eight or less orthogonal or diagonal sides can be supported using this structure.

Non-orthogonal structures and space tiles for layout, placement, and routing of an integrated circuit

Disclosed are methods and mechanisms for implementing tessellation-based processing of an integrated circuit design. Tessellation based routing of objects on an integrated circuit layout can be performed by identifying a spacing rule for tessellating at least a portion of the integrated circuit layout, forming one or more plane figures in the tessellation having one or more edges compliant with the spacing rule, the edges of the one or more plane figures forming a contour derived from a shape of a blockage object, and identifying a routing path along at least part of the one or more edges. Packing and pushing of objects may be performed using this approach.

Method and mechanism for implementing tessellation-based routing

This work is designated to provide a common frame work of test chip design for technology development and process routine monitor, called as field-configurable test structure array (FC-TSA), which can accommodate and test the various types of test structures including transistors, diodes, and resistors. To minimize the probe-pad number and fully utilize area to maximize the area design efficiency, the memory addressing design scheme is implemented to select the device-under-test in a test chip. With the aid of using adjustable channel width of transmission gates, the input resistance of FC-TSA cell can be parameterized and configured to match with the parasitic resistance of various test structures, moreover, the background leakage could be minimized to meet with 1nA design specification. Two types of array test structures, 12/spl times/25 and 40/spl times/25, are implemented with generic logic process to demonstrate the design feasibility. The measurements of transistor set and process monitor test structures are reviewed and corresponding models are discussed.

Field-configurable test structure array (FC-TSA): enabling design for monitor, model and manufacturability

Disclosed are improved methods and mechanisms for congestion and maximum flow analysis for routing an integrated circuit design. In one approach, maximum flow analysis is performed by tessellating a portion of a layout to form space tiles, which are used to interpret a flow graph. The flow graph comprises a set of vertices and edges. The capacity of edges in the flow graph is used to identify the maximum flow for that portion of the layout. In another approach, an edge walk is performed against a set of space tiles, in which a nearest neighbor determination is determined for each edge to perform maximum flow analysis.

Maximum flow analysis for electronic circuit design

A method of analyzing a design of an electronic circuit uses slices. The method includes generating one or more slices, each slice comprising a contiguous region of the design, and generating an set comprising one or more bins for each slice. A search for an object may be performed by determining a search area, and identifying slices containing at least a portion of the search area. For each identified slice, each object within the search area is associated with one of the bins of the set for the slice.

Zone tree method and mechanism

This paper describes a common framework of test chip design for logic technology development and routine process monitoring, referred to as a field-configurable test structure array (FC-TSA), which can accommodate and test various types of test structures including transistors, diodes, and resistors. To minimize the number of probe pads and maximize area utilization efficiency, a memory-addressing design scheme is implemented to select the device-under-test within the test chip. By adjusting channel width of transmission gates at the design stage, the input resistance of FC-TSA bit-cell can be parameterized and configured to satisfy the series resistance requirement of various test structures; moreover, the leakage current can be minimized with such a methodology to meet a 1-nA design specification. A 40 x 20 FC-TSA has been implemented by utilizing a state-of-the-art logic process to demonstrate design feasibility. The measurements of a set of transistor and process monitor test structures are reviewed and corresponding models discussed.

Field-Configurable Test Structure Array (FC-TSA): Enabling Design for Monitor, Model, and Manufacturability

This study aims to provide an integrated infrastructure for electrical-based dimensional process-window checking. The proposed infrastructure is comprised of design tools, testing programs, and analytical tools, providing an automatic and hierarchical test vehicle design flow from the design of the test structure to the analysis of the electrical test data. Symbolic parameter representation is adopted to describe the relationship between design rules and test structure parameters. This integrated infrastructure also provides a specific capability for controlling local/global layout geometry and pattern density, thereby fulfilling deep sub-micron design criteria. With the aid of this design platform, discrepancies between the design rule set, test structure design, and the testing plan are minimized. Using the function-independent Test Structure Design Intellectual Property ( TSD-IP) provided by this infrastructure, the process-window is quantitatively characterized as the electrical parameters. A cross-generation test vehicle (130-nm/90-nm nodes), used for evaluating any overlay shifts and variations in critical dimensions across the intra- and interphoto fields, has been developed to demonstrate the proposed design infrastructure.

S.P.-S. Ho

Papers

Field-Configurable Test Structure Array (FC-TSA): Enabling Design for Monitor, Model, and Manufacturability

Infrastructure development and integration of electrical-based dimensional process window checking