S
S. Patel
Researcher at Indian Institutes of Information Technology
Publications - 1
Citations - 37
S. Patel is an academic researcher from Indian Institutes of Information Technology. The author has an hindex of 1, co-authored 1 publications receiving 37 citations.
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Energy efficient design and implementation of ALU on 40nm FPGA
TL;DR: There is 67.04% dynamic power reduction with LVCMOS12 when the authors migrate from 90-nm Spartan-3 FPGA to 40-nm Virtex-6FPGA, and there is 81.19%, 92.05% and 73.41% dynamicPower reduction in ALU with LVDCI IO standard in place of LVD CI_DV2, HSTL_I, and LVCmOS12 respectively.