In this work, we are making energy efficient ALU using the most energy efficient LVCMOS IO standard for the highest frequency of i7 processor. It is observed that LVCMOS12 is the most energy efficient than all available LVCMOS having 26.23, 58.37 and 75.65 % less IO power reduction than LVCMOS18, LVCMOS25 and LVCMOS33 respectively at 1 GHz. Then we are making this ALU portable using MOBILE DDR IO standard in place of default LVCMOS33 IO standard which we use in traditional ALU. As we replace LVCMOS with MOBILE DDR, we are achieving 69.07 % portability in terms of IO power and 29.36 % in terms of Leakage power at 2.9 GHz. In next stage, we try to enhance the performance of ALU with MOBILE DDR but not beyond the power consumption with LVCMOS. In that way, we achieve the highest frequency of 12 GHz with MOBILE DDR. That was earlier possible for 3.8 GHz 64-bit ALU using CMOS. In this HDL based implementation of 64-bit ALU on FPGA, Kintex-7 FPGA is used with XC7K70T device and FBG676 package is used.

Mobile DDR IO Standard Based High Performance Energy Efficient Portable ALU Design on FPGA

Image ALU is a special type of ALU exclusively designed to perform arithmetic and logical operation on Image only. This Image ALU design is able to perform 14 operations. In this work, we have proposed a novel 4-stages energy efficient CTHS (C-Capacitance Scaling, T-Thermal Scaling, H-HSTL I/O Standard, S-SSTL I/O Standard) approach for Low Power and Thermal Aware Image ALU Design. CTHS technique is achieving 81.79 % reduction in power consumption which is more than the power reduction by method discussed in Shrivastava et al. (IEEE Trans Very Large Scale Integr Syst 18(6):988---997, 2010); Yoonjin and Mahapatra (IEEE Trans Very Large Scale Integr Syst 18(1):15---28, 2010); Chatterjee and Sachdev (IEEE Trans Very Large Scale Integr Syst 13(11):1296---1304, 2005); Wijeratne et al. (IEEE J Solid State Circuits 42(1):26---37, 2007); Nehru et al. (International conference on advances in engineering, science and management pp 145---149, 2012); Ho et al. (IEEE international symposium on circuits and systems pp 353---356, 2013); Rani et al. (3rd in international conference on electronics computer technology pp 224---228, 2011) for ALU. There is 38.63 % reduction in I/O Power and 46.42 % reduction in leakage power, when we scale down capacitance from 50 to 5 pF on 28 nm technology based Kintex-7 FPGA on 100 GHz device operating frequency. FPGA is a Filed Programmable Gate Array. There is 67.05 % reduction in I/O Power when we scale down ambient temperature from 50 to 10 °C on 100 GHz frequency. There are 5 different climates in koppen climate classification. We are taking 5 different values in order to nearly represent 5 climates. Using high profile Heat Sink and 500 LFM Airflow, there is 75.39 % leakage power reduction from the last optimized result of capacitance scaling and 85.84 % leakage power reduction from the initial power dissipation. On 3rd stage, using HSTL I/O Standard, there is 64.53 % power reduction from the initial power dissipation. There is 41.06, 59.26, 78.75 % power reduction from HSTL_II_DCI_18 to HSTL_I_12 on 100, 10 and 1 GHz. On 4th and final stage, using SSTL I/O Standard, there is 81.79 % power reduction from the initial power dissipation. There is 61.83 % reduction in junction temperature, when we apply 500 LFM airflow and high profile heat sink in compare to 250 LFM airflow and no heat sink. LFM is an acronym for Linear Feet per Minute. LFM is a unit of airflow that help us to control junction temperature of FPGA. Unit of leakage power is Watt (W) and Junction Temperature is degree Celsius (°C).

CTHS Based Energy Efficient Thermal Aware Image ALU Design on FPGA

In this paper, green Image ALU is designed in Xilinx ISE 14.6 using different IO standard of SSTL in 40nm Virtex-6 and Spartan-6 FPGA. We are comparing different SSTL IO standard to get reduction in IO power. We accomplish energy efficiency with respect to low voltage impedance, by using SSTL technology. In this entire work, we are using different classes of SSTL and observe that when image ALU operates at 1THz device operating frequency with SSTL18_I_DCI I/O Standard using virtex-6 FPGA, there is 45.55% decrease in IO power and 20.50% in Clock power as compared to SSTL18_II IO Standard. Similarly when we operate Image ALU at 1THz using Spartan-6, there is 33.31% reduction in IO power of SSTL18_I with respect to SSTL18_II Standard. There are 16 different arithmetic and logic operations in Image ALU. The Clock power, Logic power and Signal power of Image ALU remains same using Spartan-6 I/O Standard.

SSTL based green image ALU design on different FPGA

In this work, we are using Voltage Scaling as energy efficient technique to make energy efficient MBCCS. In MBCCS, whenever voltage or current of battery will under the threshold level the battery will continuing the charge if more than voltage or current threshold then battery will invoke Ring Overcharge Alarm. In Voltage Scaling, we scale down supply voltage from 1V to 0.1V, where 0.9V, 0.8V, 0.7V, 0.6V, 0.5V, 0.4V, 0.3V and 0.2V are intermediate supply voltage value. There is 92.72%, 87.50%, 98.77% and 68.24% reduction in Clock Power, Logic Power, Signal Power and IO Power on 1 THz device operating frequency when voltage is scale down from 1V to 0.1V with step size of 0.1V.

Simulation of Voltage Scaling Aware Mobile Battery Charge Controller Sensor on FPGA

Most of Exclusive-OR(XOR) logic gates on quantum-dot cellular automata(QCA) is based on configuration of 2-input, and they are hardly to be scalable and exists unbearable noise because they are only focused on decrease of latency and space. In this paper, we propose how to make a scalable logic using a wire crossing technique, and give examples of two expanded XOR gate using typical logic gates on QCA. The designed logics are simulated and show accurate output results.

http://www.sersc.org/journals/IJCA/vol8_no2/10.pdf

Design of Exclusive-OR Logic Gate on Quantum-Dot Cellular Automata

There is 67.04% dynamic power reduction with LVCMOS12 when we migrate from 90-nm Spartan-3 FPGA to 40-nm Virtex-6 FPGA. There is 81.19%, 92.05% dynamic power reduction when using LVCMOS12 in place of HSTL_II_18 and SSTL2_I_DCI respectively. We achieved 65.56%, 72.59% and 73.41% dynamic power reduction in ALU with LVDCI IO standard in place of LVDCI_DV2, HSTL_I, and LVCMOS12 respectively. There is 68.34% and 52.51% dynamic power reduction in ALU when using LVCMOS12 and LVCMOS15 in place of LVCMOS25. There is 62.45% dynamic power reduction in ALU, when we use HSTL_I in place of SSTL2_I_DCI. Power is directly proportional to frequency. With increase in frequency, there is increase in power consumption irrespective of IO standard. LVCMOS is the only IO standard, which takes less power when we upgrade our design to latest FPGA.

Energy efficient design and implementation of ALU on 40nm FPGA

In this work, we analyze the power requirement of synchronous and asynchronous VLSI circuit. There is 70.42% overall power reduction using asynchronous arithmetic circuit in place of synchronous circuits. In asynchronous, FDCE is used whereas FDRSE is used in synchronous. On 90nm Spartan-3 target device, we are taking counter as target design and arithmetic circuit is target design on 40nm Virtex-6. Power consumption is different at any frequency using synchronous or asynchronous design on Virtex-6 but same on Spartan-3. There is 1.22%, 7.86%, 45.73%, 82.01%, 89.01%, 89.86% power reduction with reduction in frequency by a factor of 10 in range of 1MHz-1THz.

Y. K. Singh

Papers

Energy efficient design and implementation of ALU on 40nm FPGA

Energy efficency of asynchronous and synchronous VLSI circuit on 40nm and 90nm FPGA