The ever-increasing demand for high-datarate wireless systems has led to a crowded electromagnetic (EM) spectrum. This demand has successively spurred the development of versatile microwave and millimeter-wave integrated components possessing high selectivity, multifunctionalities, and enhanced efficiency. These components require a class of nonreciprocal structures endowed with extra functionalities, e.g., frequency generation, wave amplification, and full-duplex communication. Space-time (ST) modulation has been shown to be a perfect candidate for high-data-rate transmission given its extraordinary capability for EM-wave engineering. ST-modulated (STM) media are dynamic, directional EM structures whose constitutive parameters vary in both space and time.

Space-Time Modulation: Principles and Applications

This paper introduces an advanced wave engineering technique based on unidirectional frequency generation and spatial decomposition in general space–time-modulated (STM) slabs. The extraordinary wave engineering provided by such slabs is comprised of unidirectional wavefront shaping, nonreciprocal frequency generation, and spatial decomposition of ST harmonics (STHs). We first derive a rigorous analytical solution for the wave scattering from general ST permittivity- and permeability-modulated (STP&PM) slabs. The analytical solution considers the most general form of spatiotemporal variation and wave incidence, i.e., oblique incidence and scattering from time-periodic spatially aperiodic/periodic STP&PM slabs. The spatial aperiodicity may be utilized for further spectrum engineering and suppression of undesired STHs. Next, it will be shown that an equilibrated ST refractive-index-modulated slab with equal permittivity and permeability modulation strengths exhibits highly enhanced nonreciprocity. The FDTD numerical simulation of general STM slabs is presented, providing extra leverage for the analyses of wave propagation and scattering in such media. We show that oblique incidence to an STM slab yields nonreciprocal spatial decomposition of generated STHs. The explored peculiar properties of STM slabs under oblique incidence is expected to pave the way for the realization of new class of subharmonic generators, radars, illusion cloaks, and spatial mixers and isolators.

Advanced Wave Engineering via Obliquely Illuminated Space-Time-Modulated Slab

This paper overviews the principles, theoretical analysis and numerical simulation of STM media and their applications in communication systems. We first present a global perspective on the principles of ST modulation, naturally and artificially created STM media and their applications in communication systems. Next, the interaction of artificial STM media with electromagnetic waves is analyzed, and numerical simulation of electromagnetic wave propagation and scattering from these media is provided. Then, the dispersion diagram of the STM medium is studied for the characterization of subluminal, luminal and superluminal ST modulations. In addition, we investigate the effect of length, modulation velocity, modulation frequency, and equilibrium on wave scattering from the STM medium. The extraordinary interaction of the STM medium with electromagnetic waves leads to unidirectional frequency generation and amplification, which are leveraged for the realization of various enhanced-efficiency broadband microwave components that are integrable with circuit technology, lightweight, tunable, and low cost. These applications include, but are not limited to, magnet-free isolators, magnet-free circulators, transceiver front-ends, and pure frequency mixers.

Design methodology for ultrahigh-speed 5-2 and 7-2 compressors has been illustrated in this article. With the help of introduced procedure, the gate-level delay has been reduced considerably when compared with the previous designs, while the total transistor and gate count remain in a reasonable range. By starting the discussion for the carry rippling problem in $n-2$ compressors, the method has been developed for 5-2 compressor and is expanded for 7-2 architecture, which shows 32% and 30% improvement in speed performance for these structures, respectively. Also, the careful design considerations have been taken into account to keep other characteristics, such as power and active, are at a reasonable level. Moreover, for a fair comparative conclusion, the best-reported circuits have been redesigned, and their parasitic elements were extracted utilizing the same technology employed for the synthesis of the proposed circuits. Finally, a typical $16 \times 16$ bit multiplier has been implemented to investigate the efficiency of the designed compressor blocks. Based on the postlayout simulation results provided using HSPICE for TSMC 0.18- $\mu \text{m}$ standard CMOS technology and 1.8-V power supply, the proposed compressors demonstrate better speed performance and power–delay product (PDP) factor over previous works. As the results depict, the delay of 303 ps has been achieved for the 5-2 compressor while the measured delay of the designed 7-2 compressor is 464 ps.

Very Fast, High-Performance 5-2 and 7-2 Compressors in CMOS Process for Rapid Parallel Accumulations

Multipliers are important components that dictate the overall arithmetic circuits' performance. The most critical components of multipliers are compressors. In this paper, a new 5:2 compressor architecture based on changing some internal equations is proposed. In addition, using an efficient full-adder (FA) block is considered to have a high-speed compressor. The number of transistors in the proposed design is less than the best existing 5:2 compressor architectures. Three 5:2 compressors are considered for comparison. The proposed architecture is compared with the best existing designs presented in the state-of-the-art literature in terms of power, delay and area. Architectures are simulated in 90-nm CMOS technology under 1 V supply voltage. The simulation results show that the proposed compressor improves power and delay by 24.59% and 18.54% respectively, compared to two of the best existing architectures. In addition, voltage scaling and temperature analysis show that the proposed architecture outperforms the other designs from power-delay product (PDP) point of view in comparison to the aforementioned designs.

High-speed energy-efficient 5:2 compressor

This paper presents a new high speed, low power 5-2 compressor which is constructed according to a sensible combination of pass transistor logics and static logics. The 5-2 compressor is designed based on a new truth table that is obtained by performing some changes on its conventional truth table. So simple structures are obtained in which capacitances of middle stages are decreased. Therefore, a reduction of power dissipation and a reduction of overall latency are achieved. Also, the input and internal driving problems have been decreased, considerably. Because of similar paths from inputs to the outputs, there will be no need for extra buffers in low latency paths to equalize the delays. Therefore, the power dissipation will be decreased and the output waveforms will be glitch-free. Furthermore, utilizing voltage full swing logics in these architectures has enhanced the speed of cascaded operations. The total latency and power dissipation of the proposed 5-2 compressor are about 302 ps and 248.62 μw, respectively, which is simulated by HSPICE using TSMC 0.18 μm CMOS technology.

CMOS implementation of a new high speed, glitch-free 5-2 compressor for fast arithmetic operations

This paper presents a design of a tunable inductor on silicon substrate utilizing varactor based tuning method. Varactor based tuning method is realized by adding a varactor between one of the inductor's ports and the ground. By changing admittance of the whole network and based on the value of capacitor and tuning range of varactor, maximum tuning percentage at desired frequency will vary. Wide tuning range, simplicity of design and ease of prediction, optimization and manufacturing process are advantages of this tuning method.

Varactor based tunable inductor design

In this paper design and simulation of a 6-bit KA-Band RF MEMS phase shifter in presented. In order to combine both loaded line and switch line phase shifters, a new 4-state switch is proposed. The proposed 4-state enables 3 different phase shifting. Simulation results indicate that insertion loss is less than −2.34dB and matching is better than −16.1dB for each switching state. The coverd area is 28mm2 and actuation voltage of the switch is 8.5 volt. Rms phase error is 2.07.

A ka-band phase shifter based on a new four-state MEMS switch

In this paper, a counter based all digital frequency divider is presented. The architecture is based on a counter and a control logic which controls the division ratio. Depending on the control logic circuitry, phase shifting of divided clock signal is also possible. By utilizing both divided signal and shifted signal, fractional ratios are implemented. Phase shifting relies on division factor. Key circuit of the architecture is counter that consumes more power than control logic. Depending on circuitry of the counter, power consumption could be optimized. Multiple division ratios are possible to be implemented by utilizing an appropriate control structure. The circuits were simulated in standard TSMC 0.18 um CMOS technology with nominal power supply of 1.8v.

http://ieeexplore.ieee.org/iel7/6971894/6999486/06999533.pdf

Saeed Akbari

Papers

CMOS implementation of a new high speed, glitch-free 5-2 compressor for fast arithmetic operations

Varactor based tunable inductor design

A ka-band phase shifter based on a new four-state MEMS switch

New all digital frequency divider and phase shifter