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Design Of Analog Cmos Integrated Circuits

AGIPD (Adaptive Gain Integrating Pixel Detector) is currently under development for the European X-ray Free Electron Laser (XFEL). It is a hybrid pixel detector with a specifi cally developed readout chip bump bonded to a silicon sensor. The chip is being designed in IBM 0.13 µm CMOS technology. This paper is focused on the readout chip design. The main challenges for this chip are: the high dynamic range (1 - 1.4× 10 4 ) with single photon sensitivity, the long storage chain (≥ 200) with a long hold time (99 ms), and the high radiation dose (up to 100 MGy). A charge integrating amplifier with a gain adaptive to the number of in coming photons is combined with a correlated double sampling (CDS) buffer to achieve the required dynamic range and single photon sensitivity. Several techniques are implemented in the storage cell design in order to reduce lea kage current and signal-dependent charge injection. Four prototype chips have been designed for testing the performance of the implemented switches, capacitors, amplifiers, storage cells and periphery circuitry. The recently submit ted test chip has a 16× 16 pixel matrix , 100 storage cells in each pixel and a periphery circuitry for accessing and contr olling the pixels and storage cells.

Challenges in chip design for the AGIPD detector

Probability y statistics

This paper presents the implementation of a single piece of macro fiber composite (MFC) piezoelectric transducer as a multifunctional device for both strain sensing and energy harvesting for the first time in the context of an energy harvesting powered wireless sensing system The multifunction device is achieved via time-multiplexing operation for alternating dynamic strain sensing and energy harvesting functions at different time slots associated with different energy levels, that is, when there is insufficient energy harvested in the energy storage for powering the system, the MFC is used as an energy harvester for charging up the storage capacitor; otherwise, the harvested energy is used for powering the system and the MFC is used as a strain sensor for measuring dynamic structural strain A circuit is designed and implemented to manage the single piece of MFC as the multifunctional device in a time-multiplexing manner, and the operation is validated by the experimental results The dynamic strains measured by the MFC in the implemented system match a commercial strain sensor of extensometer by 955 to 9999%, and thus the studied method can be used for autonomous structural health monitoring of dynamic strain

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Single Piezoelectric Transducer as Strain Sensor and Energy Harvester Using Time-Multiplexing Operation

An amplifier may include a low noise auto-zero circuit with auto-zero capacitors and switch-controlled auxiliary capacitors that function as switched-capacitor low-pass filters. In an acquisition phase of the auto-zero operation, the inputs of an amplifier may be shorted to a common voltage, and a representation of the offset voltage may be acquired by the auto-zero capacitors. In a hold phase of the auto-zero operation, the auto-zero capacitors may be connected to the auxiliary capacitors, and the resulting voltages may be applied to the circuit such that the original offset voltage is cancelled. Moreover, the switched-capacitor filters may reduce the effective sampling noise while maintaining high acquisition bandwidth.

Low noise auto-zero circuits for amplifiers

This paper presents a new high speed, low power 5-2 compressor which is constructed according to a sensible combination of pass transistor logics and static logics. The 5-2 compressor is designed based on a new truth table that is obtained by performing some changes on its conventional truth table. So simple structures are obtained in which capacitances of middle stages are decreased. Therefore, a reduction of power dissipation and a reduction of overall latency are achieved. Also, the input and internal driving problems have been decreased, considerably. Because of similar paths from inputs to the outputs, there will be no need for extra buffers in low latency paths to equalize the delays. Therefore, the power dissipation will be decreased and the output waveforms will be glitch-free. Furthermore, utilizing voltage full swing logics in these architectures has enhanced the speed of cascaded operations. The total latency and power dissipation of the proposed 5-2 compressor are about 302 ps and 248.62 μw, respectively, which is simulated by HSPICE using TSMC 0.18 μm CMOS technology.

CMOS implementation of a new high speed, glitch-free 5-2 compressor for fast arithmetic operations

This paper presents a high speed Single-Stage latched comparator which is scheduled in time for both amplification and latch operations. Small active area besides desired power consumption at high comparison rates qualifies the proposed comparator to be repeatedly employed in high speed flash A/D converters. A strategy of kickback noise elimination besides gain enhancement is also introduced. A low power holding Read-Out circuit is presented. Post-Layout simulation results confirm 500MS/s comparison rate with 5mv resolution for a 1.6v peak-to-peak input signal range and 600µw power consumption from a 3.3v power supply by using TSMC model of 0.35µm CMOS technology. Total active area of proposed comparator and Read-Out circuit is about 300µm2.

High-speed low-power Single-Stage latched-comparator with improved gain and kickback noise rejection

A new open-loop high-speed CMOS sample-and-hold is presented. Based on new method for further reduction of voltage-dependent charge injection, a new CMOS sample-and-hold was designed. Simulation results confirm the effectiveness of this method. Over 10 dB improvement in signal-to-noise ratio, compared to the signal-to-noise ratio of conventional bottom plate sampling S/Hs was achieved with this method. A comparison between newly designed S/H and the bottom-plate sampling S/H is presented.

A novel open-loop high-speed CMOS sample-and-hold

This paper presents a high speed single-stage latched comparator which is scheduled in time for both amplification and latch operations. Small active area and simple switching strategy besides desired power consumption at high comparison rates qualifies the proposed comparator to be repeatedly employed in high speed flash A/D converters. A strategy of kickback noise elimination besides gain enhancement is also introduced. A low power holding read-out circuit is presented. Post-Layout simulation results confirm 500MS/s comparison rate with 5mv resolution for a 1.6v peak-to-peak input signal range and 600µw power consumption from a 3.3v power supply by using TSMC model of 0.35µm CMOS technology. Total active area of proposed comparator and read-out circuit is about 300µm2.

Morteza Mousazadeh

Papers

CMOS implementation of a new high speed, glitch-free 5-2 compressor for fast arithmetic operations

High-speed low-power Single-Stage latched-comparator with improved gain and kickback noise rejection

A novel open-loop high-speed CMOS sample-and-hold

A 500 MS/s 600 µW 300 µm 2 Single-Stage Gain-Improved and Kickback Noise Rejected Comparator in 0.35 µm 3.3 v CMOS Process

A high-speed, power efficient, dead-zone-less phase frequency detector with differential structure