Exploring and identifying structure is even more important for multivariate data than univariate data, given the difficulties in graphically presenting multivariate data and the comparative lack of parametric models to represent it. Unfortunately, such exploration is also inherently more difficult.

Multivariate Density Estimation

Year 2009 marks the completion of 50 years of the invention of CORDIC (coordinate rotation digital computer) by Jack E. Volder. The beauty of CORDIC lies in the fact that by simple shift-add operations, it can perform several computing tasks such as the calculation of trigonometric, hyperbolic and logarithmic functions, real and complex multiplications, division, square-root, solution of linear systems, eigenvalue estimation, singular value decomposition, QR factorization and many others. As a consequence, CORDIC has been utilized for applications in diverse areas such as signal and image processing, communication systems, robotics and 3-D graphics apart from general scientific and technical computation. In this article, we present a brief overview of the key developments in the CORDIC algorithms and architectures along with their potential and upcoming applications.

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50 Years of CORDIC: Algorithms, Architectures, and Applications

From the Publisher: 
This is undoubtedly the most accessible book on digital signal processing (DSP) available to the beginner. Using intuitive explanations and well-chosen examples, this book gives you the tools to develop a fundamental understanding of DSP theory. The author covers the essential mathematics by explaining the meaning and significance of the key DSP equations. Comprehensive in scope, and gentle in approach, the book will help you achieve a thorough grasp of the basics and move gradually to more sophisticated DSP concepts and applications.

数字信号处理 = Understanding digital signal processing

Although arithmetic coding offers extremely high coding efficiency, it provides little or no security as traditionally implemented. We present a modified scheme that offers both encryption and compression. The system utilizes an arithmetic coder in which the overall length within the range [0,1) allocated to each symbol is preserved, but the traditional assumption that a single contiguous interval is used for each symbol is removed. Additionally, a series of permutations are applied at the input and the output of the encoder. The overall system provides simultaneous encryption and compression, with negligible coding efficiency penalty relative to a traditional arithmetic coder

Secure Arithmetic Coding

Many countries will experience the effects of an aging population, resulting in a high demand of healthcare facilities. Development of novel biomedical technologies is an urgent necessity to improve diagnostic services for this demographic. Electrocar diogram (ECG) and temperature recording have been used for more than 50 years in medical diagnosis to understand various biological activities [1], [2]. A more recent development, electronic pill technology, requires the integration of more complex systems on the same platform when compared to conventional implantable systems. A small miniaturized electronic pill can reach areas such as the small intestine and can deliver real time video images wirelessly to an external console. Figure 1 shows an electronic pill system (i.e., wireless endoscopy) for a medical monitoring system. The device travels through the digestive system to collect image data and transfers the data to a nearby computer for display with a distance of one meter or more. A high resolution videobased capsule endoscope produces a large amount of data, which can then be delivered over a high-capacity wireless link.

Easy-to-Swallow Wireless Telemetry

JPEG2000 is a new image compression standard known for its rich set of features, impressive compression performance as well as its complexity for efficient hardware implementation. Discrete wavelet transform (DWT) and embedded block coder (BC) are two main modules in JPEG2000 compression system. Data transfer between the DWT and BC modules presents challenges due to difference in data format generated by the DWT and data format accepted by the BC module. This paper investigates data transfer and storage techniques between the DWT and BC modules. The paper proposed an efficient memory organization and a data transfer scheme to reduce the data bandwidth. A VLSI architecture for the proposed data transfer (DT) system is proposed and synthesized for TSMC 0.18 mum process. Simulation results show that the proposed techniques result in an aggregate reduction in the bandwidth requirement by a factor of four for the BC module while incurring an extra hardware cost of only 5%

Efficient Data Transfer Techniques and VLSI architecture for DWT-Block Coder Integration of JPEG2000 Encoder

Optimization of On-Chip Interconnect Signaling for Low Energy and High Performance

This paper presents the design of a 212 Mb/s chip for Vertical Bell Labs Layered Space-Time (V-BLAST) detection for a 4 x 4 16-QAM MIMO wireless communication system based on the QR factorization technique. We employ Coordinate Rotation Digital Computer (CORDIC) rotator processors for pre decoder block. We implement back substitution Symbol Interference Cancellation (SIC) block without the use of division and multiplication hardware, reducing the hardware cost, without compromising the numerical stability. The proposed VLSI architecture on a 0.18 mum Application Specific Integrated Circuits (ASIC) platform achieves a throughput of 212 Mb/s with an equivalent gate count of 70 k with a core of 1 mm2 at 140 MHz clock frequency.

A 212 Mb/s Chip for 4 × 4 16-QAM V-BLAST decoder

This paper presents a novel detector implementation that takes advantage of instantaneous channel states by switching between Space-Time Coding (STC) and Spatial Multiplexing (SM) modes. For a fixed rate, the detector calculates whether the channel is better suited for SM or STC transmission. This decision can then be fed back to the transmitter via a low-rate feedback channel. The detector is designed for a 2 × 2 multiple-input multiple-output (MIMO) system and implemented on an Altera Cyclone II FPGA.

An adaptive Space-Time Coding / Spatial Multiplexing detector on FPGA

This paper presents the implementation of a single FPGA intellectual property (IP) core for channel coding and interleaving used in Digital Video Broadcasting, second generation (DVB-T2). DVB-T2 is the extension of the television standard DVB-T, issued by the consortium DVB, and is devised for the broadcast transmission of digital terrestrial television. The higher offered bit rate, with respect to its predecessor DVB-T, makes it a suited system for carrying high definition TV (HDTV) signals on the terrestrial TV channel. In this paper we specifically target the version suitable for China Multimedia Mobile Broadcast (CMMB) standard that works on the 2,635 to 2,660 MHz frequency band to provide 25 video and 30 audio channels. The main contribution is the design and development of forward error correction (FEC) part for mobile multimedia broadcast system, its estimation of power dissipation and optimization. The FEC part includes Reed Solomon (RS) encoder and byte interleaver, low density parity check (LDPC) encoder and bit interleaver. All these sub-modules have been implemented and integrated for the target device Stratix III E (EP3SE50F780C4N). The design has been coded in verilog-HDL and synthesized using Quartus II 8.1 software tool. PowerPlay Power Analyzer tool provided by Altera with Quartus II software has been used for the estimation of power dissipation. Stratix III logic array block level programmable power technology and clock gating technique has been used for power optimization.

Saeid Nooshabadi

Papers

Efficient Data Transfer Techniques and VLSI architecture for DWT-Block Coder Integration of JPEG2000 Encoder

Optimization of On-Chip Interconnect Signaling for Low Energy and High Performance

A 212 Mb/s Chip for 4 × 4 16-QAM V-BLAST decoder

An adaptive Space-Time Coding / Spatial Multiplexing detector on FPGA

Efficient implementation of channel coding and interleaver for Digital Video Broadcasting (DVB-T2) on FPGA