Contemporary hardware implementations of artificial neural networks face the burden of excess area requirement due to resource-intensive elements such as multiplier and non-linear activation functions. The present work addresses this challenge by proposing a resource-efficient Co-ordinate Rotation Digital Computer (CORDIC)-based neuron architecture (RECON) which can be configured to compute both multiply-accumulate (MAC) and non-linear activation function (AF) operations. The CORDIC-based architecture uses linear and trigonometric relationships to realize MAC and AF operations respectively. The proposed design is synthesized and verified at 45nm technology using Cadence Virtuoso for all physical parameters. Implementation of the signed fixed-point 8-bit MAC using our design, shows 60% less area, latency, and power product (ALP) and shows improvement by 38% in area, 27% in power dissipation, and 15% in latency with respect to the state-of-the-art MAC design. Further, Monte-Carlo simulations for process-variations and device-mismatch are performed for both the proposed model and the state-of-the-art to evaluate expectations of functions of randomness in dynamic power variation. The dynamic power variation for our design shows that worst-case mean is $189.73\mu W$ which is 63% of the state-of-the-art.

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RECON: Resource-Efficient CORDIC-Based Neuron Architecture

Most of the scientific operation involve floating point computations. It is necessary to implement faster multipliers occupying less area and consuming less power. Multipliers play a critical role in any digital design. Even though various multiplication algorithms have been in use, the performance of Vedic multipliers has not drawn a wider attention. Vedic mathematics involves application of 16 sutras or algorithms. One among these, the Urdhva tiryakbhyam sutra for multiplication has been considered in this work. An IEEE-754 based Vedic multiplier has been developed to carry out both single precision and double precision format floating point operations and its performance has been compared with Booth and Karatsuba based floating point multipliers. Xilinx FPGA has been made use of while implementing these algorithms and a resource utilization and timing performance based comparison has also been made.

FPGA implementation of vedic floating point multiplier

Floating point multiplication is a crucial operation in high power computing applications such as image processing, signal processing etc. And also multiplication is the most time and power consuming operation. This paper proposes an efficient method for IEEE 754 floating point multiplication which gives a better implementation in terms of delay and power. A combination of Karatsuba algorithm and Urdhva-Tiryagbhyam algorithm (Vedic Mathematics) is used to implement unsigned binary multiplier for mantissa multiplication. The multiplier is implemented using Verilog HDL, targeted on Spartan-3E and Virtex-4 FPGA.

An efficient floating point multiplier design for high speed applications using Karatsuba algorithm and Urdhva-Tiryagbhyam algorithm

Binary multiplication is an important operation in many high power computing applications and floating point multiplier designs. And also multiplication is the most time, area and power consuming operation. This paper proposes an efficient method for unsigned binary multiplication which gives a better implementation in terms of delay and area. A combination of Karatsuba algorithm and Urdhva-Tiryagbhyam algorithm (Vedic Mathematics) is used to implement the proposed unsigned binary multiplier. Karatsuba algorithm is best suited for higher bits and Urdhva-Tiryagbhyam algorithm is best for lower bit multiplication. A new algorithm by combining both helps to reduce the drawbacks of both. The multiplier is implemented using Verilog HDL, targeted on Spartan-3E and Virtex-4 FPGA.

An efficient binary multiplier design for high speed applications using Karatsuba algorithm and Urdhva-Tiryagbhyam algorithm

Approximate computing is one of the most trending topics for research since the introduction of error-resilient applications. Approximate arithmetic helps reduce the power consumption, hardware utilization and delay time at the expense of accuracy. Out of all arithmetic operations, multiplication is the most widely used and it forms the crucial section in many applications. Therefore, it is necessary to optimize it as per the requirement of a system. This paper proposes an algorithm for approximate multiplication based on Karatsuba multiplication method which is compared with an existing approximate hybrid Wallace tree multiplier and it is found that the proposed approximate Karatsuba multiplier is better than existing approximate hybrid Wallace Tree multiplier in terms of hardware, latency as well as accuracy. The performance of proposed multiplier is also evaluated with the help of a application of image processing and it is found that proposed multiplier gives similar results as exact multiplier unit. Both the multipliers are implemented in Verilog HDL using Vivado 2018.3.

Approximate Karatsuba multiplier for error-resilient applications

This paper presents an efficient floating point multiplier using Karatsuba algorithm Digital signal processing algorithms and media applications use a large number of multiplications, which is both time and power consuming We have used IEEE 754 format for binary representation of the floating point numbers Verilog HDL is used to implement Karatsuba multiplication algorithm which is technology independent pipelined design This multiplier implements the significant multiplication along with sign bit and exponent computations Three stage pipelining is being used in the design with the latency of 8 clock cycles In this design, the mantissa bits are divided into three parts of particular bit width in such a way so that the multiplication can be done using the standard multipliers available in FPGA cyclone II device family and synthesized using Altera-Quartus II

Implementation of single precision floating point multiplier using Karatsuba algorithm

The concept of reconfigurable computing facilitates flexibility of the software along with high performance of hardware. The FPGA based hardware provides bit level or fine grain re-configurability where as ASIC based hardware is capable of course grain reconfiguration that lead to accelerated (hardware) performances with lesser re-programming time. This paper presents the implementation of a multiplication accumulation (MAC) unit which is reconfigurable with respect to word lengths of the operands. The unit is capable of processing signed and unsigned numbers as per the requirement. The sub units- multiplier, adder and sign selection units are reconfigurable, can function as independent units and together as accumulation unit. Reconfiguration with word length, throughput or data type is implemented with the help of a set of multiplexers, de-multiplexers and pipeline registers. Two implementations using different adders were compared. One design uses carry save addition in adder module and the other uses ripple carry addition. The implementation using ripple carry adder shows significant improvement in area and power consumption over the other. However, the use of carry save adder gives about 2% improvement on speed than its counterpart.

Sajeevan Joseph

Papers

Implementation of single precision floating point multiplier using Karatsuba algorithm

Comparison of architectures of a coarse-grain reconfigurable multiply-accumulate unit