Contemporary hardware implementations of artificial neural networks face the burden of excess area requirement due to resource-intensive elements such as multiplier and non-linear activation functions. The present work addresses this challenge by proposing a resource-efficient Co-ordinate Rotation Digital Computer (CORDIC)-based neuron architecture (RECON) which can be configured to compute both multiply-accumulate (MAC) and non-linear activation function (AF) operations. The CORDIC-based architecture uses linear and trigonometric relationships to realize MAC and AF operations respectively. The proposed design is synthesized and verified at 45nm technology using Cadence Virtuoso for all physical parameters. Implementation of the signed fixed-point 8-bit MAC using our design, shows 60% less area, latency, and power product (ALP) and shows improvement by 38% in area, 27% in power dissipation, and 15% in latency with respect to the state-of-the-art MAC design. Further, Monte-Carlo simulations for process-variations and device-mismatch are performed for both the proposed model and the state-of-the-art to evaluate expectations of functions of randomness in dynamic power variation. The dynamic power variation for our design shows that worst-case mean is $189.73\mu W$ which is 63% of the state-of-the-art.

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RECON: Resource-Efficient CORDIC-Based Neuron Architecture

Most of the scientific operation involve floating point computations. It is necessary to implement faster multipliers occupying less area and consuming less power. Multipliers play a critical role in any digital design. Even though various multiplication algorithms have been in use, the performance of Vedic multipliers has not drawn a wider attention. Vedic mathematics involves application of 16 sutras or algorithms. One among these, the Urdhva tiryakbhyam sutra for multiplication has been considered in this work. An IEEE-754 based Vedic multiplier has been developed to carry out both single precision and double precision format floating point operations and its performance has been compared with Booth and Karatsuba based floating point multipliers. Xilinx FPGA has been made use of while implementing these algorithms and a resource utilization and timing performance based comparison has also been made.

FPGA implementation of vedic floating point multiplier

Floating point multiplication is a crucial operation in high power computing applications such as image processing, signal processing etc. And also multiplication is the most time and power consuming operation. This paper proposes an efficient method for IEEE 754 floating point multiplication which gives a better implementation in terms of delay and power. A combination of Karatsuba algorithm and Urdhva-Tiryagbhyam algorithm (Vedic Mathematics) is used to implement unsigned binary multiplier for mantissa multiplication. The multiplier is implemented using Verilog HDL, targeted on Spartan-3E and Virtex-4 FPGA.

An efficient floating point multiplier design for high speed applications using Karatsuba algorithm and Urdhva-Tiryagbhyam algorithm

Adders are basic building blocks of any processor or data path application. For the design of high performance processing units high speed adders with low power consumption is a requirement. Carry Select Adder (CSA) is known to be one of the fastest adders used in many data processing applications. In this paper, we present a new CSA architecture using Manchester carry chain(MCC) in multioutput domino CMOS logic. It employs a novel MCC blocks in an hierarchical approach in the design of the CSA. The proposed design is validated by implementation of 16 and 32-bit adder circuits in a standard 45nm CMOS process technology. This proposed work evaluates the performance of the proposed designs in terms of delay, power consumption and hardware overhead. The results are analyzed and compared with existing fast adder architectures to prove its efficiency. The simulation results shows that the proposed architecture achieves two fold advantages in terms of power-delay product (PDP) and hardware overhead.

High Speed Power Efficient Carry Select Adder Design

Multiplier is one of the most desirable component in most of the processors designed today The speed of multiplier determines the speed of the processor So there is a need of high speed multiplier In this paper, a novel method for Multiplication is proposed by combining Modified Booth algorithm, Wallace tree architecture and Hybrid adder design Modified Booth Multiplier reduces the number of partial products and has least latency as compared to other multiplier designs Wallace Tree increases the speed by parallel addition of partial products Adders play an important role in addition of partial products If the speed at which the addition operation is performed is increased than the overall speed of the multiplier design will increase So the main focus in this paper is to increase the speed of the adder A novel hybrid adder design is used in the multiplier design which, has less delay and occupies less area Area, delay and power complexities of the proposed Multiplier design are reported The proposed Modified Booth Multiplier design shows better performance compare to conventional method using Carry LookAhead Adder and has advantages of reduced area overhead and critical path delay The proposed multiplier design has been synthesized using Xilinx ISE 101 design tool and simulated using ModelSim157g The programming language used is Verilog HDL

Design and implementation of high speed modified booth multiplier using hybrid adder

This paper presents an efficient floating point multiplier using Karatsuba algorithm Digital signal processing algorithms and media applications use a large number of multiplications, which is both time and power consuming We have used IEEE 754 format for binary representation of the floating point numbers Verilog HDL is used to implement Karatsuba multiplication algorithm which is technology independent pipelined design This multiplier implements the significant multiplication along with sign bit and exponent computations Three stage pipelining is being used in the design with the latency of 8 clock cycles In this design, the mantissa bits are divided into three parts of particular bit width in such a way so that the multiplication can be done using the standard multipliers available in FPGA cyclone II device family and synthesized using Altera-Quartus II

Implementation of single precision floating point multiplier using Karatsuba algorithm

The Booth multiplier is a very fast multiplier with minimum latencies. In this paper, a typical architecture of Booth Encoder and Wallace tree is presented, In which we have implemented pipelining at the intermediate nodes of the modules present in it. The architecture comprises of four modules, they are as follows, One's Complement generator, Booth Encoder, Partial product generator and Wallace tree adder accompanied by Ripple carry adder respectively. The Wallace tree adder and Booth multiplier are typically used for high speed computations. One such application is a DSP processor. In this paper we have designed a four stage pipelining at the intermediate nodes mentioned above. This will help in performing many arithmetic operations simultaneously and hence increase the speed as well as computation of simultaneous inputs. The design is implemented in Verilog HDL. The simulation is done on Cadence NC Sim while the synthesis is carried out in Cadence RTL Compiler using TSMC 45nm slow.lib.

Implementation of pipelined Booth Encoded Wallace tree Multiplier architecture

This paper proposes implementation of IEEE floating point (FP) multiplication, addition and subtraction Arithmetic on IEEE FP numbers imposes more challenges compared to fixed-point arithmetic These particularly include the simultaneous computation of normalization and rounding We show the efficient way of solving these challenges for the implementation of floating point (FP) addition, subtraction and multiplication The proposed designs aim at reducing power dissipation Here multi threshold voltage technique is used for reducing power dissipation The proposed implementations are according to the IEEE 754 FP standard

Design and implementation of low power floating point arithmetic unit

High performance digital adder with reduced area and low power consumption is an important design constraint for advanced processors The speed of operation of such an adder is limited by carry propagation from input to output Our work is based on designing an optimized adder for advanced processors This paper discusses about the implementation of Carry Select Adder combining with the possibilities of Kogge Stone Adder Kogge Stone parallel approach will give option to generate fast carry for intermediate stages The adder is implemented on Xilinx Virtex 5 FPGA devices and is compared with RCA adder and Kogge Stone adder Result shows the adder gives better performance in terms of speed and area implementation

Implementation of adder structure with fast carry network for high speed processor

This paper presents a design of 4-bit pipeline arithmetic logic unit (ALU). The novelty of the pipelined ALU is it gives high performance through the pipelining concept compare to non-pipeline ALU. Pipelining is a technique where multiple instruction executions are overlapped. The pipeline modules are independent of each other. All the modules in the ALU design are realized using verilog HDL. Design functionalities are validated through simulation and compilation. Test vectors are created to verify the outputs as opposed to the calculated results. Design simulation is done with ModelSim simulator and RTL synthesis is done with RTL Compiler tool. Physical design of this architecture is done with encounter cadence tool in 180nm technology.

P. Jayakrishnan

Papers

Implementation of single precision floating point multiplier using Karatsuba algorithm

Implementation of pipelined Booth Encoded Wallace tree Multiplier architecture

Design and implementation of low power floating point arithmetic unit

Implementation of adder structure with fast carry network for high speed processor

ASIC implementation of pipelined ALU