Quantum-dot Cellular Automata (QCA) is attracting a lot of attentions due to its extremely small feature sizes and ultra low power consumption. Up to now several designs using QCA technology have been proposed. However, we found not all of the designs function properly. Further, no general design guidelines have been proposed so far. A straightforward extension of a simple functional design pattern may fail. This makes designing a large scale circuits using QCA technology an extremely time-consuming process. In this paper we show several critical vulnerabilities in the structures of primitive QCA gates and QCA interconnects, and propose a disciplinary guideline to prevent any additional plausible but malfunctioning QCA designs.

Quantum-dot Cellular Automata Design Guideline

We establish a method for exploring the dynamics of molecular quantum-dot cellular automata (QCA) devices by hierarchically combining the techniques of quantum chemistry with the nonequilibrium time-dependent coherence vector formalism. Single QCA molecules are characterized using ab initio quantum chemistry methods. We show how to construct a simple model Hamiltonian for each QCA cell based on parameters extracted from the ab initio calculation. The model Hamiltonian captures well the relevant switching behavior and can then be used to calculate the time-dependent coherence vector, including thermal and nonequilibrium behavior. This enables us to explore dynamic behavior and power dissipation for various QCA devices and circuits.

http://absimage.aps.org/image/MAR08/MWS_MAR08-2007-006221.pdf

Molecular quantum-dot cellular automata--from molecular structure to circuit dynamics

The reduction in the operating voltage play a majorrole in improving the performance of the integratedcircuits.Apart from that lesser power consumption, reducedarea and smaller size of transistors are also the vital factors inthe design criteria and fabrication of the systems. This articleapproaches towards the increasing performance of the systemsby comparing different types of adder circuits. In this article, anew circuit has been designed using the TG technology. Basedon different parameters like average power consumption anddelay, it has been observed that the Carry look-ahead adderand Carry bypass adder consumes more power. TheComparative analysis of TG based 8-bit different AdderDesigns using 180nm technology using TANNER tool has beenconsidered.

Analysis and Comparison: Full Adder Block in Submicron Technology

Efficiency improvement of a silicon-based thin-film solar cell using plasmonic silver nanoparticles and an antireflective layer

Design of an ultra-thin silicon solar cell using Localized Surface Plasmonic effects of embedded paired nanoparticles

Quantum Dot Cellular Automata (QCA) plays a pivotal role in the emerging field of Nano electronics as well as in digital finite state machine design arena. Several gates and their proposals exist in this field all of which are recognized for their own characteristics. Majority voter is one of the several schemes of QCA. In this paper, a new gate termed as T-gate is proposed which is validated by thirteen standard functions and two input multiplexer circuit which reflects the reduction in the effective area as compared to the realization of the same by earlier methods. The T-gate can function as a universal logic gate and also as an inverter which can be realized by using fewer numbers of cells. T-gate implementation of 2×1 Multiplexer require no wire crossings and shows noticeable reduction in the cell count.

T-Gate: Concept of partial polarization in Quantum Dot Cellular Automata

Comparator is crucial block in Central Processing Unit especially in the process of “Data Searching-Sorting” where huge amount of data needs to be searched during the Database Management operations. In this work, the logic design of 1-bit Quantum Cellular Automata (QCA) comparator has been proposed using the Layered-T AND and OR Gates. The proposed comparator layout needs 9.02% less effective area compared to the best reported design so far. The effect of cell misplacements on the proposed layout is thoroughly investigated. Moreover, the other QCA design metrics such as O-Cost, CostI are calculated for the proposed 1-bit Layered T Comparator circuit. The functionality of the proposed circuit is verified by computer aided design tool QCADesigner 2.0.3.

Layered T comparator design using quantum-dot cellular automata

In the present scenario, low power, speed, and size play a significant role specifically in the field of digital VLSI circuits. The major goal of this paper is to design and implement a dig...

Performance Evaluation of Digital Comparator Using Different Logic Styles

A full adder circuit is one of the basic building blocks of a digital design. In general it is made by CMOS technology. In the CMOS technology the full adder is biult by 28 transistors. So, the transistor count is very high. The average power consumption, leakage power consumption and delay is very high. In this paper we made a new circuit which is made by mainly the Transmission Gate (TG) technology. In our circuit we use only 18 transistors to implement the Boolean Expression of the Full Adder. So, the transistor count decreases. Due to the decreasing of the transistor count we can reduces the average power, Leakage power, delay and noise. We also optimized our new circuit by different threshold of MOSFET technology.

http://ieeexplore.ieee.org/iel5/5398767/5407062/05407195.pdf

Transistor count optimization of conventional CMOS full adder & optimization of power and delay of new implementation of 18 transistor full adder by dual threshold node design with submicron channel length

The Quantum-dot Cellular Automata (QCA) is the prominent paradigm of nanotechnology considered to continue the computation at deep sub-micron regime. The QCA realizations of several multilevel circuit of arithmetic logic unit have been introduced in the recent years. However, as high fan-in Binary to Gray (B2G) and Gray to Binary (G2B) Converters exist in the processor based architecture, no attention has been paid towards the QCA instantiation of the Gray Code Converters which are anticipated to be used in 8-bit, 16-bit, 32-bit or even more bit addressable machines of Gray Code Addressing schemes. In this work the two-input Layered T module is presented to exploit the operation of an Exclusive-OR Gate (namely LTEx module) as an elemental block. The “defect-tolerant analysis” of the two-input LTEx module has been analyzed to establish the scalability and reproducibility of the LTEx module in the complex circuits. The novel formulations exploiting the operability of the LTEx module have been proposed to instantiate area-delay efficient B2G and G2B Converters which can be exclusively used in Gray Code Addressing schemes. Moreover this work formulates the QCA design metrics such as O-Cost, Effective area, Delay and Cost
 α
 for the n-bit converter layouts.

Saradindu Panda

Papers

T-Gate: Concept of partial polarization in Quantum Dot Cellular Automata

Layered T comparator design using quantum-dot cellular automata

Performance Evaluation of Digital Comparator Using Different Logic Styles

Transistor count optimization of conventional CMOS full adder & optimization of power and delay of new implementation of 18 transistor full adder by dual threshold node design with submicron channel length

QCA Gray Code Converter Circuits Using LTEx Methodology