MUCKE aims to mine a large volume of images, to structure them conceptually and to use this conceptual structuring in order to improve large-scale image retrieval. The last decade witnessed important progress concerning low-level image representations. However, there are a number problems which need to be solved in order to unleash the full potential of image mining in applications. The central problem with low-level representations is the mismatch between them and the human interpretation of image content. This problem can be instantiated, for instance, by the incapability of existing descriptors to capture spatial relationships between the concepts represented or by their incapability to convey an explanation of why two images are similar in a content-based image retrieval framework. We start by assessing existing local descriptors for image classification and by proposing to use co-occurrence matrices to better capture spatial relationships in images. The main focus in MUCKE is on cleaning large scale Web image corpora and on proposing image representations which are closer to the human interpretation of images. Consequently, we introduce methods which tackle these two problems and compare results to state of the art methods. Note: some aspects of this deliverable are withheld at this time as they are pending review. Please contact the authors for a preview.

http://ieeexplore.ieee.org/iel2/4524/12820/00592460.pdf

Image Processing

Large-scale CMPs with hundreds of cores require a directory-based protocol to maintain cache coherence. However, previously proposed coherence directories are hard to scale beyond tens of cores, requiring either excessive area or energy, complex hierarchical protocols, or inexact representations of sharer sets that increase coherence traffic and degrade performance. We present SCD, a scalable coherence directory that relies on efficient highly-associative caches (such as zcaches) to implement a single-level directory that scales to thousands of cores, tracks sharer sets exactly, and incurs negligible directory-induced invalidations. SCD scales because, unlike conventional directories, it uses a variable number of directory tags to represent sharer sets: lines with one or few sharers use a single tag, while widely shared lines use additional tags, so tags remain small as the system scales up. We show that, thanks to the efficient highly-associative array it relies on, SCD can be fully characterized using analytical models, and can be sized to guarantee a negligible number of evictions independently of the workload. We evaluate SCD using simulations of a 1024-core CMP. For the same level of coverage, we find that SCD is 13× more area-efficient than full-map sparse directories, and 2× more area-efficient and faster than hierarchical directories, while requiring a simpler protocol. Furthermore, we show that SCD's analytical models are accurate in practice.

/pdf/scd-a-scalable-coherence-directory-with-flexible-sharer-set-419bt1438h.pdf

SCD: A scalable coherence directory with flexible sharer set encoding

Genome-scale metabolic models (GEMs) have become a popular tool for systems biology, and they have been used in many fields such as industrial biotechnology and systems medicine. Since more and more studies are being conducted using GEMs, they have recently received considerable attention. However, the reliability of GEM-based predictions and analyses has remained questionable. In this review, we introduce the basic concept of GEMs and provide an overview of their applications in biotechnology, systems medicine, and some other fields. In addition, we describe the general principle of the applications and analyses built on GEMs. The purpose of this review is to introduce the application of GEMs in biological analysis and to promote its wider use by biologists.

/pdf/applications-of-genome-scale-metabolic-models-in-4k7drp97mq.pdf

Applications of Genome-Scale Metabolic Models in Biotechnology and Systems Medicine

VLSI physical design automation: theory and practice

Java programmers are faced with numerous choices in managing concurrent execution on multicore platforms. These choices often have different trade-offs (e.g., performance, scalability, and correctness guarantees). This paper analyzes an additional dimension, energy consumption. It presents an empirical study aiming to illuminate the relationship between the choices and settings of thread management constructs and energy consumption. We consider three important thread management constructs in concurrent programming: explicit thread creation, fixed-size thread pooling, and work stealing. We further shed light on the energy/performance trade-off of three ``tuning knobs'' of these constructs: the number of threads, the task division strategy, and the characteristics of processed data. Through an extensive experimental space exploration over real-world Java programs, we produce a list of findings about the energy behaviors of concurrent programs, which are not always obvious. The study serves as a first step toward improving energy efficiency of concurrent programs on parallel architectures.

/pdf/understanding-energy-behaviors-of-thread-management-2nx0a5npup.pdf

Understanding energy behaviors of thread management constructs

Motivation Synthetic lethal sets are sets of reactions/genes where only the simultaneous removal of all reactions/genes in the set abolishes growth of an organism. Previous approaches to identify synthetic lethal genes in genome-scale metabolic networks have built on the framework of flux balance analysis (FBA), extending it either to exhaustively analyze all possible combinations of genes or formulate the problem as a bi-level mixed integer linear programming (MILP) problem. We here propose an algorithm, Fast-SL, which surmounts the computational complexity of previous approaches by iteratively reducing the search space for synthetic lethals, resulting in a substantial reduction in running time, even for higher order synthetic lethals. Results We performed synthetic reaction and gene lethality analysis, using Fast-SL, for genome-scale metabolic networks of Escherichia coli, Salmonella enterica Typhimurium and Mycobacterium tuberculosis. Fast-SL also rigorously identifies synthetic lethal gene deletions, uncovering synthetic lethal triplets that were not reported previously. We confirm that the triple lethal gene sets obtained for the three organisms have a precise match with the results obtained through exhaustive enumeration of lethals performed on a computer cluster. We also parallelized our algorithm, enabling the identification of synthetic lethal gene quadruplets for all three organisms in under 6 h. Overall, Fast-SL enables an efficient enumeration of higher order synthetic lethals in metabolic networks, which may help uncover previously unknown genetic interactions and combinatorial drug targets. Availability and implementation The MATLAB implementation of the algorithm, compatible with COBRA toolbox v2.0, is available at https://github.com/RamanLab/FastSL CONTACT: kraman@iitm.ac.in Supplementary information Supplementary data are available at Bioinformatics online.

Fast-SL: an efficient algorithm to identify synthetic lethal sets in metabolic networks

Interconnect prediction is very important for early feasibility studies in modern design flows. Most of the current interconnect estimation techniques estimate either the average or the total wirelength and some qualitative measure of routing demand for circuits. A priori techniques estimate these parameters without actually performing circuit placement. We propose a new a priori interconnect and wirelength estimation methodology for island style field programmable gate arrays (FPGAs). For a given design, we estimate bounding box semiperimeter wirelengths of all nets for an optimized placement and the minimum number of tracks per channel required for successful routing on an FPGA device. We analyze the structural characteristics of circuits and limitations posed by the FPGA architecture to derive a consistent model for wirelength and routing demand estimation. We identify reconvergences present in a circuit as an important global circuit characteristic in wirelength prediction. Our overall results show that we have an average error of 11.6% w.r.t. semiperimeter wirelength measured from the optimized layout using VPR. Also, the number of routing tracks per channel is predicted with an average error of 13.2% of the detailed routing results from VPR.

/pdf/a-priori-wirelength-and-interconnect-estimation-based-on-3u5ei9b2d8.pdf

A priori wirelength and interconnect estimation based on circuit characteristics

Interconnect management is a critical design issue for large FPGA based designs. One of the most important issues for planning interconnection is the ability to accurately and efficiently predict the routability of a given design on a given FPGA architecture. The recently proposed routability estimation procedure, fGREP [6], produced estimates within 3 to 4% of an actual detailed router. Other known routability estimation methods include RISA [5], Lois's [7] method and Rent's rule based methods [1] [11] [9]. Comparing these methods has been difficult because of the different reporting methods used by the authors. We propose a uniform reporting metric based on comparing the estimates produced with the results of an actual detailed router on both local and global levels. We compare all the above methods using our reporting metric on a large number of benchmark circuits and show that the enhanced fGREP method produces tight estimates that outperform most other techniques.

/pdf/on-metrics-for-comparing-routability-estimation-methods-for-2ltw13l82u.pdf

On metrics for comparing routability estimation methods for FPGAs

Shared data synchronization is at the heart of the multicore revolution since it is essential for writing concurrent programs Ideally, a synchronization technique should be able to fully exploit the available cores, leading to improved performance However, with the growing demand for energy-efficient systems, it also needs to work within the energy and power budget of the system In this paper, we perform a detailed study of the performance as well as energy efficiency of popular shared-data synchronization techniques on a commodity multicore processor We show that Software Transactional Memory (STM) systems can perform better than locks for workloads where a significant portion of the running time is spent in the critical sections We also show how power-conserving techniques available on modern processors like C-states and clock frequency scaling impact energy consumption and performance Finally, we compare the performance of STMs and locks under similar power budgets

/pdf/the-implications-of-shared-data-synchronization-techniques-3htfdi5qet.pdf

The implications of shared data synchronization techniques on multi-core energy efficiency

Interconnect prediction is very important for early feasibility studies in modern design flows Most of the interconnect estimation techniques estimate average or total wirelength and some qualitative measure of routing demand for circuits A-priori techniques estimate these characteristics without actually performing circuit placement We propose a new a-priori interconnect and wirelength estimation methodology for island style FPGAs For a given design, we estimate bounding box lengths of all nets for an optimized placement and the minimum number of tracks per channel required for successful routing on an FPGA device We analyze the structural characteristics of circuits and limitations posed by the FPGA architecture to derive a consistent model for wirelength and routing demand estimation Our results show that we have an average error of 116% wrto bounding box spans measured from the optimized layout using VPR [2] Also, the number of routing tracks is predicted with an average error of 61% of the detailed routing results from VPR

Shankar Balachandran

Papers

Fast-SL: an efficient algorithm to identify synthetic lethal sets in metabolic networks

A priori wirelength and interconnect estimation based on circuit characteristics

On metrics for comparing routability estimation methods for FPGAs

The implications of shared data synchronization techniques on multi-core energy efficiency

A-priori wirelength and interconnect estimation based on circuit characteristics