An object is to provide a semiconductor device of which a manufacturing process is not complicated and by which cost can be suppressed, by forming a thin film transistor using an oxide semiconductor film typified by zinc oxide, and a manufacturing method thereof. For the semiconductor device, a gate electrode is formed over a substrate; a gate insulating film is formed covering the gate electrode; an oxide semiconductor film is formed over the gate insulating film; and a first conductive film and a second conductive film are formed over the oxide semiconductor film. The oxide semiconductor film has at least a crystallized region in a channel region.

Semiconductor device, and manufacturing method thereof

Thin films are formed by formed by atomic layer deposition, whereby the composition of the film can be varied from monolayer to monolayer during cycles (301) or (450, 455, 460, 470) including alternating pulses of self-limiting chemistries. In the illustrated embodiments, varying amounts of impurity sources (306 or 460) are introduced during the cyclical process. A graded gate dielectric (72) is thereby provided, even for extremely thin layers. The gate dielectric (72) as thin as 2 nm can be varied from pure silicon oxide to oxynitride to silicon nitride. Similarly, the gate dielectric (72) can be varied from aluminum oxide to mixtures of aluminum oxide and a higher dielectric material (e.g., ZrO2) to pure high k material and back to aluminum oxide. In another embodiment, metal nitride (432) (e.g., WN) is first formed as a barrier for lining dual damascene trenches and vias. During the alternating deposition process, copper can be introduced, e.g., in separate pulses, and the copper source pulses (460) can gradually increase in frequency, forming a graded transition region (434), until pure copper (436) is formed at the upper surface. Advantageously, graded compositions in these and a variety of other contexts help to avoid such problems as etch rate control, electromigration and non-ohmic electrical contact that can occur at sharp material interfaces.

Graded thin films

A three-dimensional sense adjusting unit displays three-dimensional images to a user. If a displayed reaches a limit of parallax, the user responds to the three-dimensional sense adjusting unit. According to acquired appropriate parallax information, a parallax control unit generates parallax images to realize the appropriate parallax in the subsequent stereo display. The control of parallaxes is realized by optimally setting camera parameters by going back to three-dimensional data. Functions to realize the appropriate parallax are made into and presented by a library.

Method and apparatus for processing three-dimensional images

A system includes a semiconductor device. The semiconductor device includes a first single crystal silicon layer comprising first transistors, first alignment marks, and at least one metal layer overlying the first single crystal silicon layer, wherein the at least one metal layer comprises copper or aluminum more than other materials; and a second single crystal silicon layer overlying the at least one metal layer. The second single crystal silicon layer comprises a plurality of second transistors arranged in substantially parallel bands. Each of a plurality of the bands comprises a portion of the second transistors along an axis in a repeating pattern.

System comprising a semiconductor device and structure

A device comprising semiconductor memories, the device comprising: a first layer and a second layer of layer-transferred mono-crystallized silicon, wherein the first layer comprises a first plurality of horizontally-oriented transistors; wherein the second layer comprises a second plurality of horizontally-oriented transistors; and wherein the second plurality of horizontally-oriented transistors overlays the first plurality of horizontally-oriented transistors.

Semiconductor device and structure

A semiconductor metalization barrier, and manufacturing method therefor, is provided which is a stack of a cobalt layer and cobalt tungsten layer deposited on a copper bonding pad.

Semiconductor metalization barrier

Manufacturing method for semiconductor metalization barrier

The texture of electroplated Cu lines of 0.375, 0.5 and 1.5 μm widths with Ta and TiN barrier layers was analyzed using x-ray pole figure and electron backscatter diffraction (EBSD) techniques. Both techniques indicate a strong (111) fiber texture relative to the bottom surface of the trench for samples with a Ta barrier layer and a 400 °C, 30 min, postelectroplating anneal. Samples with a TiN barrier and no anneal exhibit a weak (111) texture. For both barrier layers the quality of the texture, as measured by (111) peak intensity, fraction of randomly oriented grains and (111) peak width, degrades with decreasing linewidth. EBSD data also indicate (111) texture relative to the sidewalls of the trench in samples with a Ta barrier and postelectroplating anneal. Electromigration tests at 300 °C of 0.36 μm damascene Cu lines with the same process conditions show that samples with very weak (111) texture have median time to failures that exceed those of the strongly textured Cu lines. These results indicate t...

Texture analysis of damascene-fabricated Cu lines by x-ray diffraction and electron backscatter diffraction and its impact on electromigration performance

An integrated circuit and method of fabrication is provided for an integrated circuit having punch-through suppression. Unlike conventional methods of punch-through suppression wherein a dopant implant is fabricated in the device, the present invention utilizes an inert ion implantation process whereby inert ions are implanted through a fabricated gate structure on the semiconductor substrate to form a region of inert ion implant between source and drain regions of a device on the integrated circuit. This accumulation region prevents punch-through between source and drain regions of the device. In a second embodiment, the inert ion implantation is used in conjunction with the conventional punch-through dopant implant. In this second embodiment, diffusion of the implant during subsequent thermal annealing is suppressed by the inert ion accumulation in the subsurface region of the device. Accordingly, improved integrated circuits and methods of fabricating an integrated circuit having punch-through suppression are disclosed.

Method of fabricating an integrated circuit having punch-through suppression

Copper interconnects with enhanced electromigration are formed by filling a via/contact hole and/or trench in a dielectric layer with undoped Cu. A Cu layer containing a dopant element, such as Pd, Zr or Sn is deposited on the undoped Cu contact/via and/or line. Annealing is then conducted to diffuse the dopant element into the copper contact/via and/or line to improve its electromigration resistance. CMP is then performed.

Shekhar Pramanick

Papers

Semiconductor metalization barrier

Manufacturing method for semiconductor metalization barrier

Texture analysis of damascene-fabricated Cu lines by x-ray diffraction and electron backscatter diffraction and its impact on electromigration performance

Method of fabricating an integrated circuit having punch-through suppression

Copper interconnect methodology for enhanced electromigration resistance