Transition metal silicides represent an extremely broad set of refractory materials that are currently employed for many applications including CMOS devices, thin film coatings, bulk structural components, electrical heating elements, photovoltaics, and thermoelectrics. Many of these applications may be improved by making 1-dimensional nanomaterials. Chemical synthesis of silicide nanowires is more complicated compared to other classes of nanomaterials due to the complex phase behaviour between metals and silicon and the complex stoichiometries and structures of their resulting compounds. Recently, several synthetic strategies have been developed to overcome this challenge resulting in increasing reports of silicide nanowires in the literature. These strategies are highlighted in this feature article, along with future synthetic challenges and a review of the applications emerging from current silicide nanowires.

Synthesis and applications of metal silicide nanowires

Ultralong, single-crystal Ni2Si nanowires sheathed with amorphous silicon oxide were synthesized on a large scale by a chemical vapor transport (CVT) method, using iodine as the transport reagent and Ni2Si powder as the source material. Structural characterization using powder X-ray diffraction, electron microscopy, and energy-dispersive spectroscopy shows that the nanowires have Ni2Si−SiOx core−shell structure with single-crystal Ni2Si core and amorphous silicon oxide shell. The oxide shell is electrically insulating and can be removed by HF etching. Four-terminal electrical measurements show that the single-crystal nanowire has extremely low resistivity of 21 μΩ·cm and is capable of supporting remarkably high failure current density >108 A/cm2. These unique Ni2Si nanowires are very attractive nanoscale building blocks for interconnects and fully silicided (FUSI) gate applications in nanoelectronics.

Ultralong single-crystal metallic Ni2Si nanowires with low resistivity.

We report the synthesis, structural characterization, and electrical transport properties of free-standing single-crystal CoSi nanowires synthesized via a single-source precursor route. Nanowires with diameters of 10−150 nm and lengths of greater than 10 μm were synthesized through the chemical vapor deposition of Co(SiCl3)(CO)4 onto silicon substrates that were covered with 1−2 nm thick SiO2. Transmission electron microscopy confirms the single-crystal structure of the cubic CoSi. X-ray absorption and emission spectroscopy confirm the chemical identity and show the expected metallic nature of CoSi, which is further verified by room-temperature and low-temperature electrical transport measurements of nanowire devices. The average resistivity of CoSi nanowires is found to be about 510 μΩ cm. Our general and rational nanowire synthesis approach will lead to a broad class of silicide nanowires, including those metallic materials that serve as high-quality building blocks for nanoelectronics and magnetic semi...

Metallic Single-Crystal CoSi Nanowires via Chemical Vapor Deposition of Single-Source Precursor

The development of semiconductor nanowires has recently been the focus of extensive research as these structures may play an important role in the next generation of nanoscale devices. Using semiconductor nanowires as building blocks, a number of high performance electronic devices have been fabricated. In this review, we discuss synthetic methodologies and electrical characteristics of Si, Ge, and Ge/Si core/shell nanowires. In particular the fabrication and electrical properties of a variety of nanowire-based field effect transistors (FETs) are discussed. Although the bottom-up approach has the potential to go far beyond the limits of top-down technology, new techniques need to be developed to realize precise control of structural parameters, such as size uniformity, growth direction, and dopant distribution within nanowires to produce nanowire-based electronics on a large scale.

Synthesis and electrical and mechanical properties of silicon and germanium nanowires

Contact metals (Au, Ir, and Cr) are deposited on bulk WSe2 under ultra-high vacuum (UHV, 1 × 10−9 mbar) and high vacuum (HV, 5 × 10−6 mbar) conditions and subsequently characterized with x-ray photoelectron spectroscopy (XPS) to elucidate the effects of reactor base pressure on resulting interface chemistry, contact chemistry, and band alignment. Au forms a van der Waals interface with WSe2 regardless of deposition chamber ambient. In contrast, Ir and Cr form a covalent interface by reducing WSe2 to form interfacial metal selenides. When Cr is deposited under HV conditions, significant oxygen incorporation is observed resulting in the thermodynamically favorable formation of tungsten oxyselenide and a substantial concentration of Cr x O y . Regardless of contact metal, WO x (2.63 < x < 2.92) forms during deposition under HV conditions which may positively affect interface transport properties. Cr and Ir form unexpectedly large electron and hole Schottky barriers, respectively, when deposited under UHV conditions due to interfacial reactions that contribute to anomalous band alignment. These results reveal the true interface chemistry formed between metals and WSe2 under UHV and HV conditions and demonstrate the impact on the Fermi level position following contact formation on WSe2.

https://iopscience.iop.org/article/10.1088/2053-1583/aa6bea/pdf

WSe2-contact metal interface chemistry and band alignment under high vacuum and ultra high vacuum deposition conditions

Metal silicides continue to play an indispensable role during the remarkable development of microelectronics. Along with several other technological innovations, the implementation of the self-aligned silicide technology paved the way for a rapid and successful miniaturization of device dimensions for metal–oxide–semiconductor field-effect transistors (MOSFETs) in pace with the Moore’s law. The use of silicides has also evolved from creating reliable contacts for diodes, to generating high-conductivity current paths for local wiring, and lately to forming low-resistivity electrical contacts for MOSFETs. With respect to the choice of silicides for complementary metal–oxide–semiconductor (CMOS) technology, a convergence has become clear with the self-alignment technology using only a limited number of silicides, namely TiSi2, CoSi2, and NiSi. The present work discusses the advantages and limitations of TiSi2, CoSi2, and NiSi using the development trend of CMOS technology as a measure. Specifically, the reactive diffusion and phase formation of these silicides in the three terminals of a MOSFET, i.e., gate, source, and drain, are analyzed. This work ends with a brief discussion about future trends of metal silicides in micro/nanoelectronics with reference to potential material aspects and device structures outlined in the International Technology Roadmap for Semiconductors.

Self-aligned silicides for Ohmic contacts in complementary metal–oxide–semiconductor technology: TiSi2, CoSi2, and NiSi

According to a first aspect of the present innovation there is provided a semiconductor based integrated sensor device comprising: a lateral insulating-gate field effect transistor (MOSFET) connected in series to the base of a vertical bipolar junction transistor (BJT) wherein the drain-drift-region of said MOSFET is part of the base-region of the BJT within the semiconductor substrate thus making electrical contact to the base of the BJT and the distance of the drain-drift-region of the MOSFET to the emitter of the BJT exceeds the vertical distance between the emitter and any buried layer, serving as collector, and the breakdown voltage of the device being determined by the BVCEO of the vertical BJT.

An integrated sensor device for charge detection

A semiconductor based integrated sensor device includes: a lateral insulating-gate field effect transistor (MOSFET) connected in series to the base of a vertical bipolar junction transistor (BJT) wherein the drain-drift-region of the MOSFET is part of the base-region of the BJT within the semiconductor substrate thus making electrical contact to the base of the BJT and the distance of the drain-drift-region of the MOSFET to the emitter of the BJT exceeds the vertical distance between the emitter and any buried layer, serving as collector, and the breakdown voltage of the device being determined by the BV CEO of the vertical BJT.

Integrated circuit sensor device for charge detection hybridizing a lateral metal oxide semiconductor field effect transistor (MOSFET) and a vertical bipolar junction transistor (BJT)

Shili Zhang

Papers

Self-aligned silicides for Ohmic contacts in complementary metal–oxide–semiconductor technology: TiSi2, CoSi2, and NiSi

An integrated sensor device for charge detection

Integrated circuit sensor device for charge detection hybridizing a lateral metal oxide semiconductor field effect transistor (MOSFET) and a vertical bipolar junction transistor (BJT)