International Journal of Computer and Applications

An improved DWT-SVD domain watermarking for medical information security

Resistive random access memory (RRAM) devices are receiving increasing extensive attention due to their enhanced properties such as fast operation speed, simple device structure, low power consumption, good scalability potential and so on, and are currently considered to be one of the next-generation alternatives to traditional memory. In this review, an overview of RRAM devices is demonstrated in terms of thin film materials investigation on electrode and function layer, switching mechanisms and artificial intelligence applications. Compared with the well-developed application of inorganic thin film materials (oxides, solid electrolyte and two-dimensional (2D) materials) in RRAM devices, organic thin film materials (biological and polymer materials) application is considered to be the candidate with significant potential. The performance of RRAM devices is closely related to the investigation of switching mechanisms in this review, including thermal-chemical mechanism (TCM), valance change mechanism (VCM) and electrochemical metallization (ECM). Finally, the bionic synaptic application of RRAM devices is under intensive consideration, its main characteristics such as potentiation/depression response, short-/long-term plasticity (STP/LTP), transition from short-term memory to long-term memory (STM to LTM) and spike-time-dependent plasticity (STDP) reveal the great potential of RRAM devices in the field of neuromorphic application.

https://www.mdpi.com/2079-4991/10/8/1437/pdf

Advances of RRAM Devices: Resistive Switching Mechanisms, Materials and Bionic Synaptic Application.

With the widespread growth of medical images and improved communication and computer technologies in recent years, authenticity of the images has been a serious issue for E-health applications. In order to this, various notable watermarking techniques are developed by potential researchers. However, those techniques are unable to solve many issues that are necessary to be measured in future investigations. This paper surveys various watermarking techniques in medical domain. Along with the survey, general concepts of watermarking, major characteristics, recent applications, concepts of embedding and recovery process of watermark, and the summary of various techniques (in tabular form) are highlighted in brief. Further, major issues associated with medical image watermarking are also discussed to find out research directions for fledgling researchers and developers.

Watermarking techniques for medical data authentication: a survey

On Degree Based Topological Properties of Two Carbon Nanotubes

Cover dependent watermarking against ambiguity attacks

The Leakage power, performance, data retentation, and stability are the key challenges in Static Random Access Memory (SRAM) at Deep-Sub-Micron (DSM) CMOS technology. In the DSM technology, when threshold voltage, channel length, and gate oxide thickness are reduced, leakage currents in deep sub-micrometer regimes causes power dissipation in CMOS digital circuits which may affect the data ability and stability in the SRAM. In this work the effect of supply voltage has been observed in the IP3 SRAM Bit-Cell using N-Curve methodology at the room temperature (RT). To see the effect of supply voltage variations on the stability and ability parameters in the 6T and IP3 SRAM Bit-Cells, the supply voltage has been varied from 0.6V to 1.0V in step of 0.1V. It has been seen that the read, write stability and ability are comparable in both cells at RT. The other design parameters taken from the CMOS technology available on 45nm are as tOX = 2.4 nm, Vthn = 0.224 V, and Vthp = 0.24 V at RT = 27°C.

/pdf/effect-of-supply-voltage-on-ability-and-stability-in-ip3-szlaks17mv.pdf

Effect of Supply Voltage on Ability and Stability in IP3 SRAM Bit-Cell at 45nm CMOS Technology using N-Curve

Excellent thermal conductivities, superior current capabilities and ballistic transport operation these prominent properties of carbon nanotube field-effect transistor technology make it superior or alternative approach over traditional CMOS and conventional FETs. A detailed simulation-based analysis of this technology with the evaluation of circuit performance of SRAM is presented here. Performance of CNTFET-based 6T SRAM and 7T SRAM is analyzed and compared in terms of static noise margin and static power dissipation. Variations of parameters for performance evaluation include fermi level, dielectric constant, oxide thickness, work function and chiral vector. The work has modelled in HSPICE software using Stanford CNTFET model for channel length of 32, 22, 16 and 7 nm. Evaluated results show that CNTFET-based 7T-SRAM has high static noise margins when compared with 6T-SRAM.

Performance Evaluation and Comparison of CNTFET-Based 7T SRAM with 6T SRAM

The data stability issues in SRAM cells become more prominent with the decreasing of feature sizes in CMOS technology. The focus of memory manufacturers always remains on reducing power consumption and stability improvements of the SRAM cells. In this work, the critical parameters of FinFET and CMOS transistors based on SRAM cells are compared. This paper focuses on the simulation of 10T SRAM cell topologies design using sleep transistor, drowsy cache, and self-controllable voltage technique (SVL) techniques and their comparison. Among all these techniques, SVL shows the best results by consuming 4768 nw power for FinFET technology and 15.8383 n W power for CMOS technology. Evaluated results show 40%, 26%, and 10% improvement in HSNM, RSNM, and WSNM, respectively, and 80.93% reduction in leakage power. FinFET design SRAM cells result in higher RSNM, HSNM, and WSNM. For simulation, the HSPICE tool is used at 32 nm PTM CMOS and FinFET transistor with a supply voltage of 900 mV and 25 °C temperature.

Shilpi Birla

Papers

Cover dependent watermarking against ambiguity attacks

Effect of Supply Voltage on Ability and Stability in IP3 SRAM Bit-Cell at 45nm CMOS Technology using N-Curve

Performance Evaluation and Comparison of CNTFET-Based 7T SRAM with 6T SRAM

Comparative Study of CMOS and FinFET-Based SRAM Cell Using SVL Technique