International Journal of Computer and Applications

An improved DWT-SVD domain watermarking for medical information security

Resistive random access memory (RRAM) devices are receiving increasing extensive attention due to their enhanced properties such as fast operation speed, simple device structure, low power consumption, good scalability potential and so on, and are currently considered to be one of the next-generation alternatives to traditional memory. In this review, an overview of RRAM devices is demonstrated in terms of thin film materials investigation on electrode and function layer, switching mechanisms and artificial intelligence applications. Compared with the well-developed application of inorganic thin film materials (oxides, solid electrolyte and two-dimensional (2D) materials) in RRAM devices, organic thin film materials (biological and polymer materials) application is considered to be the candidate with significant potential. The performance of RRAM devices is closely related to the investigation of switching mechanisms in this review, including thermal-chemical mechanism (TCM), valance change mechanism (VCM) and electrochemical metallization (ECM). Finally, the bionic synaptic application of RRAM devices is under intensive consideration, its main characteristics such as potentiation/depression response, short-/long-term plasticity (STP/LTP), transition from short-term memory to long-term memory (STM to LTM) and spike-time-dependent plasticity (STDP) reveal the great potential of RRAM devices in the field of neuromorphic application.

https://www.mdpi.com/2079-4991/10/8/1437/pdf

Advances of RRAM Devices: Resistive Switching Mechanisms, Materials and Bionic Synaptic Application.

With the widespread growth of medical images and improved communication and computer technologies in recent years, authenticity of the images has been a serious issue for E-health applications. In order to this, various notable watermarking techniques are developed by potential researchers. However, those techniques are unable to solve many issues that are necessary to be measured in future investigations. This paper surveys various watermarking techniques in medical domain. Along with the survey, general concepts of watermarking, major characteristics, recent applications, concepts of embedding and recovery process of watermark, and the summary of various techniques (in tabular form) are highlighted in brief. Further, major issues associated with medical image watermarking are also discussed to find out research directions for fledgling researchers and developers.

Watermarking techniques for medical data authentication: a survey

On Degree Based Topological Properties of Two Carbon Nanotubes

The High leakage current in deep sub-micrometer region is becoming a significant contributor to power dissipation in CMOS circuits as threshold voltage, channel length, and the gate oxide thickness are reduced. As the standby current in memories is critical in low-power design. By lowering the supply voltage (VDD) to its standby limit, the data retention voltage (DRV), SRAM leakage power can be reduced substantially. The DRV increases with transistor mismatches. In this paper, we demonstrated the drowsy cache technique which shows a decrease in the leakage current dissipation in deep sub-micron designs of memory cells and embedded memories. The focus of this work is to simulate an effective scheme for SRAM leakage suppression in battery-powered mobile applications.

Analysis and Simulation of a Low Leakage Conventional SRAM Memory Cell at Deep Sub-micron Level

Bio-Implantable Microsystems such as the cardiac pacemaker, retinal and neural implant provides substitute for a missing biological part, support an impaired biological structure or even upgrade the existing biological system. These microsystems require ultra-low power miniature integrated circuit technology for long term reliable operation. For energy constraint applications like the implantable devices, the performance requirement are secondary factors while energy efficiency, low power, high density and high robustness are of primary concern. For low power operation, scaling the supply voltage into sub-threshold region is possible and is an effective technique for power reduction. Implantable devices require minimum energy consumption and prolonged battery lifetime. So these systems demand low leakage currents without sacrificing much on performance. In this work a new 9T MTIP3 SRAM Bit-Cell is proposed at 45nm CMOS technology using multi-threshold (MTCMOS) design technique. The static power saving in MTIP3 is 99.83% as compared to conventional 6T and 23.82% as compared to IP3 at VDD=0.8V. The dynamic power saving of read1 in MTIP3 is 86.37% as compared to 6T. The dynamic power saving of write1 in MTIP3 is 66.23% as compared to IP3. The access time of MTIP3 is 16.94% less than 6T. The energy saving during hold mode in MTIP3 is 99.5% as compared to 6T. Static Noise Margins are improved by 2.07% compared to IP3 at VDD =0.7V.

/pdf/design-and-analysis-of-a-novel-ultra-low-power-sram-bit-cell-gfzpk5bx7c.pdf

Design and Analysis of a Novel Ultra-Low Power SRAM Bit-Cell at 45nm CMOS Technology for Bio-Medical Implants

This paper presents a single-ended 11T sub-threshold SRAM (SE11T) based on 10-nm FinFET technology. The performance of the proposed design is evaluated and compared with those of other state-of-the-art SRAMs namely 6T, 8T, DIRP10T, ST2, PPN10T, and FC11T at VDD = 0.3 V. The proposed design improves read stability by 2.08X/1.31X/1.03X compared to 6T/ST2/PPN10T due to the read-decoupling technique. Furthermore, it improves writability by 1.42X/2.85X/1.35X/1.28X compared to 6T/DIRP10T/ST2/PPN10T owing to feedback-cutting scheme. The use of write bitline free structure make the proposed SRAM consumes at least 2.79X lower dynamic power. The static power is reduced in the proposed SRAM by at least 1.09X. The reduction is because of the stacking of the transistors, the long path from power VDD to ground, and eliminated leakage in read path. The proposed SRAM works reliably even when exposed to extreme process variations. The proposed bitcell occupies a 1.46X/1.19X higher area than that of 6T/8T. The proposed design improves most of the design metrics and can be an efficient candidate for portable applications with budgeted power. 

FinFET-based 11T sub-threshold SRAM with improved stability and power

In traditional verification environment, hardware and software involve isolated design and verification. Due to the demise of Moore's law, the processor's frequency is no longer increasing. This de...

UVM-powered hardware/software co-verification

Spiral Inductor is becoming a crucial element for the increasing demands of the emerging wireless communication designs. Yet, the challenges of modeling spiral inductors for narrow-band applications are increasing along with emerging Ultra-Wideband (UWB) wireless applications. The challenge is to get an accurate model for UWB applications. A characterization using simulation offers more flexibility during the design process of the spirals. This approach also avoids the need for a specific test wafer dedicated to the spirals, a process parameter characterization suffices. As simulation adds predictive nature in the design process, changes can be made more easily to optimize and fine-tune the layout of the spiral for an optimal inductance value and quality factor. This optimization process can even be automated. Parameter studies can reveal sensitivities and insight on how to improve the behavior of the spiral. A simulation-based approach requires an accurate, computationally efficient and user-friendly tool. This paper discusses integrated spiral inductor metrics, key physical design challenges, and current modeling approaches and limitations. It introduced a new EM solver for introduces a new spiral inductor modeling methodology and application example that is well suited to UWB wireless applications.

Shilpi Birla

Papers

Analysis and Simulation of a Low Leakage Conventional SRAM Memory Cell at Deep Sub-micron Level

Design and Analysis of a Novel Ultra-Low Power SRAM Bit-Cell at 45nm CMOS Technology for Bio-Medical Implants

FinFET-based 11T sub-threshold SRAM with improved stability and power

UVM-powered hardware/software co-verification

New Modeling Technology for Spiral Inductors for Ultra Wideband Applications