S
Shuhei Mitani
Researcher at Rohm
Publications - 25
Citations - 528
Shuhei Mitani is an academic researcher from Rohm. The author has contributed to research in topics: Dielectric & Irradiation. The author has an hindex of 11, co-authored 25 publications receiving 446 citations.
Papers
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Proceedings ArticleDOI
High performance SiC trench devices with ultra-low ron
Takashi Nakamura,Yuki Nakano,Masatoshi Aketa,Ryota Nakamura,Shuhei Mitani,H. Sakairi,Y. Yokotsuji +6 more
TL;DR: In this article, the authors have developed SiC trench structure Schottky diodes and SiC double-trench MOSFETs to improve device performance by reducing the electric field through the introduction of the aforementioned trench structures.
Journal ArticleDOI
Investigation of unusual mobile ion effects in thermally grown SiO2 on 4H-SiC(0001) at high temperatures
Atthawut Chanthaphan,Takuji Hosoi,Shuhei Mitani,Yuki Nakano,Takashi Nakamura,Takayoshi Shimura,Heiji Watanabe +6 more
TL;DR: In this paper, the generation and elimination of mobile ions in thermally grown SiO2 on 4H-SiC (0001) was systematically investigated by electrical measurements of MOS capacitors.
Journal ArticleDOI
Energy Band Structure of SiO2/4H-SiC Interfaces and its Modulation Induced by Intrinsic and Extrinsic Interface Charge Transfer
Heiji Watanabe,Takashi Kirino,Yusuke Kagei,J. R. Harries,Akitaka Yoshigoe,Yuden Teraoka,Shuhei Mitani,Yuki Nakano,Takashi Nakamura,Takuji Hosoi,Takayoshi Shimura +10 more
TL;DR: In this article, the energy band structure of SiO2/4H-SiC fabricated on (0001) Si- and (000-1) C-face substrates was investigated by means of synchrotron radiation x-ray photoelectron spectroscopy (SR-XPS).
Journal ArticleDOI
690V, 1.00 mΩcm2 4H-SiC Double-Trench MOSFETs
TL;DR: In this article, the double-trench MOSFET was proposed to improve the oxide destruction at the trench bottom during high drain-source voltage application, which has both source trenches and gate trenches.
Proceedings ArticleDOI
Performance and reliability improvement in SiC power MOSFETs by implementing AlON high-k gate dielectrics
Takuji Hosoi,Shuji Azumo,Yusaku Kashiwagi,Shigetoshi Hosaka,Ryota Nakamura,Shuhei Mitani,Yuki Nakano,Hirokazu Asahara,Takashi Nakamura,Tsunenobu Kimoto,Takayoshi Shimura,Heiji Watanabe +11 more
TL;DR: In this paper, the thickness ratio of the AlON layer to the SiO 2 interlayer and nitrogen content in AlON film were carefully optimized to enhance device performance and reliability.