This paper presents two voltage controlled oscillators (VCOs) operating at 5.42 and 5.76 GHz implemented in 0.18-μm complementary metal-oxide semiconductor (CMOS) technology with integrated passive device (IPD) inductors. One IPD inductor was stacked on the top of the active region of the 5.76-GHz VCO chip, whereas the other IPD inductor was placed on the top of the 5.42-GHz VCO CMOS chip but far from the its active region. The high-quality IPD inductors reduce the phase noise of the VCOs. The measurements of the two VCOs indicate the same phase noise of -120 dBc/Hz at 1 MHz offset frequency. These results demonstrate a 6-dB improvement compared to the VCO using an on-chip inductor. This paper also presents the effect of the coupling between the IPD inductor and the active region of the chip on the phase noise performance.

Low Phase Noise and Low Power Consumption VCOs Using CMOS and IPD Technologies

Transmission lines are fundamental elements in millimeter-wave circuits. In this paper, on-chip coupled transmission lines, fabricated in a commercial 0.18 ?m complementary metal-oxide semiconductor process, have been modeled, based on measured 50 GHz four-port scattering-parameters. The two-port open-short deembedding technique and thru deembedding method were successfully extended and applied to the four-port structures presented here. The accuracy of the deembedding techniques was verified by full-wave electromagnetic simulation. Based on the deembedded S-parameters, a SPICE-compatible equivalent circuit model of on-chip coupled transmission lines was extracted. Simulation and measurement results agree well over the entire frequency band from 100 MHz up to 50 GHz.

On-Chip Coupled Transmission Line Modeling for Millimeter-Wave Applications Using Four-Port Measurements

This paper develops a novel design method for synthesizing the multi-passband filter with high flexibility in various passband location and fractional bandwidth. Using the proposed compensation technology in the equivalent circuit of multi-passband resonator, the cutoff frequencies and matching property in passband regions can be improved. Tripleand quad-band bandpass filters operating in both wireless local area network (WLAN) 802.11 a/b/g and worldwide interoperability for microwave access (WiMAX) systems are presented to verify the design method. The lumped-element coplanar waveguide stub fabricated by the split-ring resonator is established to realize filter with compact size. All the measured, full-wave simulated and equivalent-circuit modeled results illustrate a good agreement among them, which validates the multi-passband design methodology and shows the advantages of DC elimination and deep rejection between each passband.

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Synthesis of triple-band and quad-band bandpass filters using lumped-element coplanar waveguide resonators

A dual-band antenna-in-package for millimeter-wave (mmW) applications is presented in the paper. The proposed antenna, which consists of a radiating slot and an air-filled cavity, is fed by a microstrip loaded with two tuning open-circuited stubs through a coupling C-shape aperture to achieve dual-band characteristics. The air-filled cavity, which is formed by the space between CMOS chip and integrated passive device substrate after flip-chip assembly process, can reduce loss and improve antenna gain. Simulation and measurement regarding antenna reflection coefficient, radiation pattern, and peak gain are conducted for design validation. The measured results show that the antenna can operate in V-band and E-band, and the impedance bandwidths with the reflection coefficient less than -10 dB are 6.1% and 5.8%, respectively. The measured gains are -2 dBi at 58 GHz and 0.3 dBi at 77 GHz, respectively. The proposed antenna is well suited for dual-band mmW high-data-rate wireless communication systems.

Design of Dual-Band Millimeter-Wave Antenna-in-Package Using Flip-Chip Assembly

We make suspended inductors and 2.45 GHz BPFs on the selectively anodized aluminum. The thick anodized alumina is used as the supporting dielectric and it is easily removed by using chemical wet-etching. The thickness of anodized alumina is 80 mum and the depth of the total air-cavity is 200 mum. The fabricated inductor over an air cavity has a 25% greater Q factor and 21% higher inductance at 2 GHz compared to an inductor on anodized aluminum. The 2.45 GHz BPF adjusting the suspended inductors has 2.8 dB of insertion loss with a narrow bandwidth.

Suspended Spiral Inductor and Band-Pass Filter on Thick Anodized Aluminum Oxide

An integrated passive device (IPD) technology has been developed to meet the ever increasing needs of size and cost reduction in radio front-end transceiver module applications. Electromagnetic (EM) simulation was used extensively in the design of the process technology and the optimization of inductor and harmonic filter designs and layouts. Parameters such as inductor shape, inner diameter, metal thickness, metal width, and substrate thickness have been optimized to provide inductors with high quality factors. The technology includes 1) a thick plated gold metal process to reduce resistive loss; 2) MIM capacitors using PECVD SiN dielectric layer; 3) airbridges for inductor underpass and capacitor pick-up; and 4) a 10 mil finished GaAs substrate to improve inductor quality factor. Both lumped element circuit simulations and electromagnetic (EM) simulations have been used in the harmonic filter circuit designs for high accuracy and fast design cycle time. This paper will present the EM simulation calibration and demonstrate the importance of using EM simulation in the filter design in order to achieve first-time success in wafer fabrication. The fabricated IPD devices have insertion loss of 0.5 dB and harmonic rejections of 30dB with die size of 1.42 mm for high band (1710 MHz-1910 MHz) and 1.89 mm for low band (824-915 MHz) harmonic filters.

Compact Harmonic Filter Design and Fabrication Using IPD Technology

An integrated passive device (IPD) on GaAs technology has been developed to meet the ever increasing needs of size and cost reduction in radio transmit module applications. Extensive electromagnetic (EM) simulations were used in the design of process technology and the optimization of inductor and harmonic filters design and layout. Parameters such as inductor shape, inner diameter, metal thickness, metal width and substrate thickness have been optimized to provide inductors with high quality factors. The technology includes the following features: 1) thick plated gold metal process to reduce resistive loss; 2) MIM capacitors using PECVD Si/sub 3/N/sub 4/ dielectric layer; 3) airbridges for inductor underpass and capacitor pick-up; and 4) 10mil finished GaAs substrate to improve inductor quality factor. Both lumped element circuit simulation and electromagnetic (EM) simulations have been used in the harmonic filter circuit design for fast design cycle time and high accuracy. This paper presents the EM simulation calibration and demonstrate the importance of using EM simulations in filter design in order to achieve success in first wafer fabrication. The fabricated IPD devices have insertion loss of 30dB with die size of 1.42mm/sup 2/ for high band (1710MHz -1910MHz) and 1.89mm/sup 2/ for low band (824MHz-915MHz) harmonic filters.

Compact harmonic filter design and fabrication using IPD technology

In conventional TRL (thru-reflection-line) de-embedding technique, a test fixturing, which mimics the traces (called adaptor) leading to a DUT (device under test), is fabricated. The TRL de-embedding procedure is performed on the test fixturing to obtain the calibration coefficients. Using the coefficients stored in the test instrument, the test instrument can thus report true characteristics (two-port s-parameter matrix, for example) of the DUT (Lucyszyn et al., 1992 and Pla et al.1995). The TRL de-embedding technique is accurate only when the test fixturing is identical to the adaptor of the DUT in both length and configuration. However, in some situations, such as a multi-I/O DUT (for example, a switch SP4T that has one input and 4 outputs) with only ONE set of TRL de-embedding fixturing, the accuracy of the DUT measurement could be inaccurate. For example, the coupling of the adaptor on the DUT test vehicle could be artificially added to or subtracted from the DUT, if the TRL de-embedding fixtures are not identical in both length and configuration to the adaptors connected to the DUT. The reported isolation characteristic of the DUT is thus inaccurate. In this article, a post processing de-embedding technique, which employs directly electrical property of the adaptor, is proposed. The postprocessing formulation was described and validated. The technique is then used to illustrate that the isolation of a DUT can be inaccurately reported if the TRL de-embedding fixturing is different from the adaptor of the DUT.

A Post-Processing De-Embedding Technique and Effect of TRL Measurement Using an Incorrect Fixturing

Compact harmonic low and high band filters for RF front-end transmit modules using an IPD technology are demonstrated. These filters exhibit excellent performance with insertion loss below 0.5 dB and harmonic rejection close to or greater than 20 dB over the entire frequency band. This paper also discusses the general design methodology for the cost-effective and efficient design of such devices.

Compact low and high band harmonic filters using an integrated passives device (IPD) technology

Miniaturization of consumer electronic devices is increasing demands to reduce the size of Power Management Integrated Circuit (PMIC) devices. In addition, the integration of additional functionality on a single chip is increasing the package's I/O count. As a result, the packages for these devices are continuously reducing in size and lead pitch. The need to improve R ON performance is pushing the capability limits of some of the current package solutions. The Wafer Level Chip Scale Package (WLCSP) is a viable option to meet these needs. This solution provides a small geometry, lightweight package with improved electrical and thermal performance compared to other available package technologies. However, as the WLCSP technology proliferates into new applications and markets, developers need to be continually aware of the limitations. For analog and power management devices, understanding the impact and limitations with the associated high current needs is imperative. Recent research is showing that as solder ball pitches and sizes decrease, the study of electromigration and solder joint reliability is crucial to ensuring the reliability of analog / PMIC devices in WLCSPs [1]. This paper summarizes recent work done to assess electromigration performance of lead-free WLCSP solder bumps.

Shun-Meen Kuo

Papers

Compact Harmonic Filter Design and Fabrication Using IPD Technology

Compact harmonic filter design and fabrication using IPD technology

A Post-Processing De-Embedding Technique and Effect of TRL Measurement Using an Incorrect Fixturing

Compact low and high band harmonic filters using an integrated passives device (IPD) technology

High-sensitivity electromigration testing of lead-free WLCSP solder bumps