A method and system are described to reduce process variation as a result of the semiconductor processing of films in integrated circuit manufacturing processes. The described methods use process variation and electrical impact to modify the design and manufacture of integrated circuits.

Characterization adn reduction of variation for integrated circuits

Variations are characterized in feature dimensions of an integrated circuit that is to be fabricated in accordance with a design by a process that produces topographical variation in the integrated circuit, the variations in feature dimension being caused by the topographical variations. The process includes lithography or etch. Predicted characteristics are verified to conform to the design, the characteristics including feature dimensions or electrical characteristics. A process is selected for use in fabricating the integrated circuit based on the relative predicted variations. Chip-level features of a design of an integrated circuit are verified for manufacture within focus limitations of a lithographic tool. Whether a design of a level of an integrated circuit can be lithographically imaged in accordance with the design is predicted, and if it cannot be, the design or processing parameters are adjusted so that it can be.

Characterization and verification for integrated circuit designs

A method and system are described to reduce process variation as a result of the electrochemical deposition (ECD), also referred to as electrochemical plating (ECP), and chemical mechanical polishing (CMP) processing of films in integrated circuit manufacturing processes. The described methods use process variation and electrical impact to direct the insertion of dummy fill into an integrated circuit.

Dummy fill for integrated circuits

Subtleties of advanced fabrication processes and nano-scale phenomena associated with integrated circuit miniaturization have exposed the insufficiencies of design rules. Such inadequacies have adverse impact on all parts of the integrated circuit creation flow where design rules are used. In addition, segregation of the various layout data modification steps required for deep sub-micrometer manufacturing are resulting in slack and inefficiencies. This invention describes methods to improve integrated circuit creation via the use of a unified model of fabrication processes and circuit elements that can complement or replace design rules. By capturing the interdependence among fabrication processes and circuit elements, the unified model enables efficient layout generation, resulting in better integrated circuits.

Design-manufacturing interface via a unified model

Use of models in integrated circuit fabrication

The correlation between inversion layer mobility of MOSFET's and surface micro-roughness of the channel has been studied using split CV measurements and AFM analysis. The mobility at high normal field decreases with increasing the surface roughness over a wide range of roughness from 0.3 nm to 4.3 nm (RMS). The trend is the same even for very thin gate oxides down to 3 nm. Careful AFM measurements are used to show that the gate oxide thickness doesn't affect the surface roughness, supporting the independence of mobility on the gate oxide thickness.

Correlation between inversion layer mobility and surface roughness measured by AFM

This work reviews and compares density and time-dependent dielectric CMP models Model fits to experimental CMP data demonstrate that a density model alone cannot explain the polishing of medium-low and low density features It is shown that time-dependent models, which take into account contact with down areas, can explain this effect These models are combined into a single model, whose parameters can be chosen to provide a 50% decrease in fitting error over that of the density model It also shown that even the combined time-density model cannot explain the polishing of certain low density features Finally, variations of this model are given which significantly reduce the number of parameters to be found, and show potential for use in predicting post-polish thicknesses for arbitrary layouts

A cmp model combining density and time dependencies

For the first time, metal–oxide–semiconductor interface atomic force microscope images were used to directly calculate the Fowler-Nordheim tunneling behavior for thin gate oxides with different interface roughness. Assuming that the roughness is conformal on both interfaces, surface curvature and electric field distribution were used to calculate the tunneling current density caused by low spatial frequency roughness. On the other hand, a three-dimensional Laplace solver and a quasi-one-dimensional Fowler-Nordheim equation were used to calculate the tunneling current contributed by high spatial frequency roughness. Considering contributions due to both high and low spatial frequency roughnesses, we found good agreement between the theoretical calculation and experimentally measured tunneling current–voltage curves. This simulation indicates that oxide thinning is probably not the main reason for the increase of tunneling current in the thin oxide (∼6 nm) range. The higher surface electric field due to rou...

Analysis of interface roughness’s effect on metal–oxide–semiconductor Fowler-Nordheim tunneling behavior using atomic force microscope images

Since a premetal dielectric (PMD) is used in the first level of interconnects, tight control of the critical dimension of the subsequent first-level contact is essential. The thickness nonuniformity due to PMD chemical mechanical polishing (CMP) can consume most of the depth-of-focus budget for the deep UV lithographic process. In this paper, we first describe a low pressure/high speed CMP process for PMD. Using a polishing pressure of only 2.5 psi, we improve the within die nonuniformity by 20-30%. To meet the throughput requirement, we can achieve a very high polish rate (>5000 A/min) by using high rotational speeds. Second, we describe an integrated noncontact clean to achieve low post-CMP defect counts and metallic contaminations. Cleaning phosphosilicate glass (PSG) is generally more difficult than undoped oxides. Because PSG is softer than an undoped oxide, it usually has more microscratches. Because phosphorous acts as a gettering center for metallic impurities, PSG can have high metallic contamination after post-CMP clean. HF immersion can greatly reduce the metallic contamination, but it enlarges the microscratches, leading to a large number of detectable defects. Mechanisms for the removal of slurry residue, microscratches, and metallic contamination are discussed in this paper.

Optimization of the Chemical Mechanical Polishing Process for Premetal Dielectrics

Microroughness is a critical parameter in ULSI device interface reliability and has been shown to effect several critical MOS electrical properties. The atomic force microscope (AFM) has become the instrument of choice for silicon surface microroughness analysis. The parameters usually specified to characterize roughness are average and root mean square roughness. However, these parameters are spatial averages and can have the same value for two significantly different surfaces. Spectral analysis using the Fast Fourier Transform (FFT) has been applied as a powerful tool to analyze AFM data by looking at roughness as a function of spatial wavelength. The Fast Hartley Transform, being a real transform, is faster than the FFT and is better suited for this analysis. It has been used here to derive spectral information from the AFM height data. Before evaluating the transform, cancellation of any tilt or warp in the AFM data is done to remove frequency components which interfere with other spectral information. A PC-based computer program to determine the transform and its magnitude will be described. The application of this method to analyze data from Si and SiO2 surfaces as a function of pre-oxidation cleaning chemistry will be presented. Significantly better insight into the spatial distribution of roughness is obtained, when compared to previous implementations.

Simon J. Fang

Papers

Correlation between inversion layer mobility and surface roughness measured by AFM

A cmp model combining density and time dependencies

Analysis of interface roughness’s effect on metal–oxide–semiconductor Fowler-Nordheim tunneling behavior using atomic force microscope images

Optimization of the Chemical Mechanical Polishing Process for Premetal Dielectrics

Analyzing atomic force micrographs using spectral methods