Simon W. Moore

TL;DR: Simulations illustrate that dramatic cycle time improvements are possible without compromising router efficiency, and these reductions permit flits to be routed in a single cycle, maximising the effectiveness of the router's limited buffering resources.

TL;DR: It is shown that human brain structural networks, and the nervous system of the nematode C. elegans, also obey Rent's rule, and exhibit some degree of hierarchical modularity, suggesting that these principles of nervous system design are highly conserved.

TL;DR: CHERI, a hybrid capability model that extends the 64-bit MIPS ISA with byte-granularity memory protection, is presented, demonstrating that it enables language memory model enforcement and fault isolation in hardware rather than software, and that the CHERI mechanisms are easily adopted by existing programs for efficient in-program memory safety.

TL;DR: It is demonstrated how 1-of-n encoded speed-independent circuits provide a good framework for constructing smart card functions that are resistant to side channel attacks and fault injection.

TL;DR: This work demonstrates multiple orders-of-magnitude improvement in scalability, simplified programmability, and resulting tangible security benefits as compared to compartmentalization based on pure Memory-Management Unit (MMU) designs.