S
Sohiful Anuar Zainol Murad
Researcher at Universiti Malaysia Perlis
Publications - 113
Citations - 700
Sohiful Anuar Zainol Murad is an academic researcher from Universiti Malaysia Perlis. The author has contributed to research in topics: CMOS & Amplifier. The author has an hindex of 12, co-authored 111 publications receiving 565 citations. Previous affiliations of Sohiful Anuar Zainol Murad include Kyushu University & Universiti Sains Malaysia.
Papers
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Proceedings ArticleDOI
Interdigitated electrodes as impedance and capacitance biosensors: A review
N. S. Mazlan,Muhammad M. Ramli,Mohd Mustafa Al Bakri Abdullah,Dewi Suriyani Che Halin,Siti S. Mat Isa,L. F. A. Talip,N. S. Danial,Sohiful Anuar Zainol Murad +7 more
TL;DR: In this paper, the working principle and influencer of the impedance and capacitance biosensors are investigated, and the details have been discussed in detail in this paper. But, the geometry and structures of the interdigitated electrodes are not considered.
Journal ArticleDOI
An Excellent Gain Flatness 3.0–7.0 GHz CMOS PA for UWB Applications
Sohiful Anuar Zainol Murad,Ramesh K. Pokharel,A. I. A. Galal,Rohana Sapawi,Haruichi Kanaya,Keiji Yoshida +5 more
TL;DR: In this paper, the authors present an excellent gain flatness CMOS power amplifier for UWB applications at 3.0-7.0 GHz in TSMC 0.18 μm CMOS technology.
Journal ArticleDOI
Low Group Delay 3.1–10.6 GHz CMOS Power Amplifier for UWB Applications
Rohana Sapawi,Ramesh K. Pokharel,Sohiful Anuar Zainol Murad,Awinash Anand,Nischal Koirala,Haruichi Kanaya,Keiji Yoshida +6 more
TL;DR: In this article, a low group delay ultra-wideband (UWB) power amplifier in CMOS technology is proposed, which employs a three-stage cascade common source topology that has a different design concept from other multi-stage topology to provide a broad bandwidth characteristic, gain flatness of, and low group delays variation of.
Journal ArticleDOI
Carbon Nanotube and Resistive Random Access Memory Based Unbalanced Ternary Logic Gates and Basic Arithmetic Circuits
TL;DR: This work aims to demonstrate the viability of RRAM in the design of ternary logic systems and shows a very small variation in power consumption and energy consumption with variation in process parameters, temperature, output load, supply voltage and operating frequency.
Journal ArticleDOI
High efficiency, good linearity, and excellent phase linearity of 3.1-4.8 GHz CMOS UWB PA with a current-reused technique
TL;DR: The UWB PA proposed here employs cascode topology with a current-reused technique to enhance the gain at the upper end of the desired band, an inter-stage inductor, and a resistive feedback at the second stage to obtain the flatness gain.