Throughout the decades of continuous advances in semiconductor technology, from the discrete devices of the late 1950s to today's billon-transistor system-on-chip, there have always been concerns about the ability of components to operate safely in an increasingly disruptive electromagnetic environment. This paper provides a nonexhaustive review of the research work conducted in the field of electromagnetic compatibility (EMC) at the IC level over the past 40 years. It also brings together a collection of information and trends in IC technology, in order to build a tentative roadmap for the EMC of ICs until the year 2020, with a focus on measurement methods and modeling approaches.

/pdf/the-electromagnetic-compatibility-of-integrated-circuits-49xkw7fvs2.pdf

The Electromagnetic Compatibility of Integrated Circuits—Past, Present, and Future

Spread spectrum is a technique introduced for mitigating electromagnetic interference (EMI) problems in many class of circuits. In this paper, with particular emphasis on switching DC/DC converters, we consider the most common and most efficient known spreading techniques, looking for spreading parameters that ensure the highest EMI reduction and the lowest performance reduction in the circuit where the spreading is applied. The result is an interesting tradeoff not only between EMI reduction and performance drop, but also on the EMI reduction itself when considering different EMI victim models. The proposed analysis is supported by measurements on two switching DC/DC converters: 1) based on pulse-width modulation and 2) based on the resonant converter class.

EMI Reduction via Spread Spectrum in DC/DC Converters: State of the Art, Optimization, and Tradeoffs

Advances in manufacturing process technology are key ensembles for the production of integrated circuits in the sub-micrometer region. It is of paramount importance to assess the effects of tolerances in the manufacturing process on the performance of modern integrated circuits. The polynomial chaos expansion has emerged as a suitable alternative to standard Monte Carlo-based methods that are accurate, but computationally cumbersome. This paper provides an overview of the most recent developments and challenges in the application of polynomial chaos-based techniques for uncertainty quantification in integrated circuits, with particular focus on high-dimensional problems.

https://biblio.ugent.be/publication/8566050/file/8566051.pdf

Review of Polynomial Chaos-Based Methods for Uncertainty Quantification in Modern Integrated Circuits

This paper presents a new analytical model to predict upsets, which are induced by electromagnetic interferences (EMI) in CMOS operational amplifiers (opamps). In particular, it is pointed out that the demodulation of EMI, which is experienced in feedback CMOS opamps, is related to the power spectral density of the interfering signals reaching the opamp input terminals. Furthermore, the new model is employed to design a differential stage immune to EMI.

Design of an Operational Amplifier Input Stage Immune to EMI

We propose here a nondestructive electromagnetic (EM) near-field test bench for both EM compatibility and susceptibility of circuits. This setup permits both the collection of the near field and injection without contact of a disturbing EM field, all through a probe. Exhaustive characterizations of probes are undertaken via simulations and experiments. According to their design, they are supposedly linked more to the electric or the magnetic field. Simulations of their EM behavior are undergone to fix their optimal geometries, leading to the best measurement performances. It is shown by both the simulations and the S-parameter measurements that their presence does not interfere with the electric behavior of the device under test. Then, logic circuits are characterized from the EM point of view, with the help of this test bench. Circuits are placed on three different printed boards: one double-sided low-frequency board without a ground plane and two single-sided boards with a ground plane and a design that is more or less optimized. EM near-field mappings highlight the strong field areas of the circuits. The need for a ground plane is highlighted. Field patterns on the traces are linked with those observed on microstrip lines. Then, an EM aggression is injected over a supposed sensitive zone of the circuit. Whichever printed board is considered, a parasitic signal superimposes itself on the output signal of the gates. Deepened studies are undergone to exhaustively explain the phenomena observed.

Near-Field Electromagnetic Characterization and Perturbation of Logic Circuits

Electromagnetic Compatibility of Integrated Circuits: Techniques for Low Emission and Susceptibility focuseson the electromagnetic compatibility of integrated circuits. The basic concepts, theory, and an extensive historical review of integrated circuit emission and susceptibility are provided. Standardized measurement methods are detailed through various case studies. EMC models for the core, I/Os, supply network, and packaging are described with applications to conducted switching noise, signal integrity, near-field and radiated noise. Case studies from different companies and research laboratories are presented with in-depth descriptions of the ICs, test set-ups, and comparisons between measurements and simulations. Specific guidelines for achieving low emission and susceptibility derived from the experience of EMC experts are presented.

Electromagnetic Compatibility of Integrated Circuits: Techniques for low emission and susceptibility

With the growing concerns about electromagnetic compatibility of integrated circuits, the need for accurate prediction tools and models to reduce risks of noncompliance becomes critical for circuit designers. However, an on-chip characterization of noise is still necessary for model validation and design optimization. Although different on-chip measurement solutions have been proposed for emission issue characterization, no on-chip measurement methods have been proposed to address the susceptibility issues. This paper presents an on-chip noise sensor dedicated to the study of circuit susceptibility to electromagnetic interferences. A demonstration of the sensor measurement performances and benefits is proposed through a study of the susceptibility of a digital core to conducted interferences. Sensor measurements ensure a better characterization of actual coupling of interferences within the circuit and a diagnosis of failure origins.

/pdf/on-chip-noise-sensor-for-integrated-circuit-susceptibility-2569yzj679.pdf

On-Chip Noise Sensor for Integrated Circuit Susceptibility Investigations

This paper presents a methodology dedicated to modeling and simulation of low-dropout (LDO) voltage regulator susceptibility to conducted electromagnetic interference (EMI). A test chip with a simple LDO structure was designed for EMC test and analysis. A transistor-level model, validated by functional tests, Z-parameter characterization and direct power injection (DPI) measurements, is used to predict the immunity of the LDO regulator. Different levels of model extraction reveal the weight contributions of subcircuits and parasitic elements on immunity issues. The DPI measurement results show a good fit with model prediction up to 1 GHz.

/pdf/modeling-and-simulation-of-ldo-voltage-regulator-3zx5u8csr5.pdf

Modeling and Simulation of LDO Voltage Regulator Susceptibility to Conducted EMI

This paper presents the strategies used for effective teaching and skill development in integrated circuit (IC) design using project-based learning (PBL) methodologies. It presents the contexts in which these strategies are applied to IC design courses at the University of South Australia, Adelaide, Australia, and the National Institute of Applied Science (INSA), Toulouse, France. Collaborations among the faculty members of the two institutions have produced a set of learning resources and design tools to support the development of industry-relevant design skills and lifelong learning skills. At the pedagogical level, the emphasis is on the development of practical circuit design, critical thinking, and problem-solving skills rather than the mastery of complex circuit design tools. The courses enable students to learn about the most recent technological developments and their implications, using a set of user-friendly tools. The PBL methodologies, intuitive design tools, and latest technology models have consistently produced high levels of student satisfaction with the overall quality of the courses at the two institutions.

/pdf/effective-teaching-of-the-physical-design-of-integrated-1qmoe8r71f.pdf

Effective Teaching of the Physical Design of Integrated Circuits Using Educational Tools

The low dropout voltage regulator (LDO) is very sensitive to electromagnetic interference (EMI) coupled onto the power supply, with concomitant output voltage offset. Most electromagnetic compatibility analyses of the LDO do not account for the effects of ageing. However, device ageing can degrade the physical parameters of semiconductor devices and can worsen the effect of EMI. This paper analyses the drift in LDO immunity after accelerated ageing. A large number of measurements that show the variations in the test results for dc characteristic, impedance, and immunity reveal increasing susceptibility after electrical accelerated ageing.

/pdf/characterization-of-changes-in-ldo-susceptibility-after-302cnnjwnv.pdf

Sonia Ben Dhia

Papers

Electromagnetic Compatibility of Integrated Circuits: Techniques for low emission and susceptibility

On-Chip Noise Sensor for Integrated Circuit Susceptibility Investigations

Modeling and Simulation of LDO Voltage Regulator Susceptibility to Conducted EMI

Effective Teaching of the Physical Design of Integrated Circuits Using Educational Tools

Characterization of Changes in LDO Susceptibility After Electrical Stress