Journal of the ACM

A review of ground-based robotic systems for the characterization of nuclear environments

An integrated circuit (IC) module allows volatile data generated by applications to be stored within volatile data files in the volatile memory. A file system tracks the location of all data files as residing in either volatile memory or nonvolatile memory and facilitates access to the volatile data files in volatile memory in a similar manner to accessing nonvolatile data files in nonvolatile memory. The file system exposes a set of application program interfaces (APIs) to allow applications to access the data files. The same APIs are used to access both volatile data files and nonvolatile data files. When an application requests access to a data file, the file system initially determines whether the application is authorized to gain access to the data file. If it is, the file system next determines whether the data file resides in volatile memory or nonvolatile memory. Once the memory region is identified, the file system identifies the physical location of the data file.

Smart card with volatile memory file subsystem

A microcontroller, which addresses program memory separately from data memory, is disclosed. The microcontroller includes a CPU and a boot memory coupled to the CPU. A control is coupled to the CPU and to the boot memory. In a first state, the control causes the boot memory to be configured as data memory. In a second state, the control causes the boot memory to be configured as program memory. A method for loading the boot memory is also disclosed. The method includes configuring the boot memory to be addressed as data memory unless it is already configured to be addressed as data memory, loading a program from an external program memory into the boot memory, configuring the boot memory to be addressed as a program memory, and executing the program in the boot memory. A method for using the microcontroller and method to debug software is described.

Adaptable boot loader

A memory system to manage a memory using a virtual memory is provided. The memory system may use an asymmetric memory as a swap storage of a dynamic random access memory (DRAM). The asymmetric memory may access on a byte basis, allowing a process to directly access a page swapped out to the asymmetric memory through direct mapping.

Memory system and method of managing the same

A microcontroller memory system that provides on-chip, non-volatile memory for internal data and program code storage in such a manner that all on-chip, non-volatile memory is efficiently utilized In one embodiment, a microcontroller memory scheme allows internal program code (220') and data (220) stored in the non-volatile memory to be reprogrammed in place by software executing on the microcontroller or by external devices through the microcontroller's serial port In another embodiment, data and program code stored in the internal program area can be accessed using any instruction employed to access via an internal data bus the contents of an on-chip, volatile memory (230) The non-volatile memory used to store the program code and internal data can be implemented with Flash memory or EEPROM To enable compatibility with conventional 8051 controllers, a flag (242) in a special function register (240) is provided that indicates whether a memory access is to be into the non-volatile memory or, in the conventional manner, into internal volatile (230) or external volatile (212) memory used for data (as opposed to program) storage

Microcontroller virtual memory system and method

A radiation-hardened SRAM-based field programmable gate array VS1000 is designed and fabricated with a 0.5 m partial-depletion silicon-on-insulator logic process at the CETC 58th Institute. The new logic cell (LC), with a multi-mode based on 3-input look-up-table (LUT), increases logic density about 12% compared to a traditional 4-input LUT. The logic block (LB), consisting of 2 LCs, can be used in two functional modes: LUT mode and distributed read access memory mode. The hierarchical routing channel block and switch block can significantly improve the flexibility and routability of the routing resource. The VS1000 uses a CQFP208 package and contains 392 reconfigurable LCs, 112 reconfigurable user I/Os and IEEE 1149.1 compatible with boundary- scan logic for testing and programming. The function test results indicate that the hardware and software cooperate successfully and the VS1000 works correctly. Moreover, the radiation test results indicate that the VS1000 chip has total dose tolerance of 100 krad(Si), a dose rate survivability of 1.5 10 11 rad(Si)/s and a neutron fluence immunity of 1 10 14 n/cm 2 .

https://iopscience.iop.org/article/10.1088/1674-4926/32/7/075012/pdf

A radiation-hardened SOI-based FPGA

In this paper, we propose a methodology of the automated bitstream generation for conducting high-testability FPGA tests. In order to study the efficiency of our solution we will explore our methodology in the test of an SOI-based FPGA. We use a semi-automated approach of the bitstream generation for ease of test vector design with high functionality and fault coverage. The methodology from this research is extensively exercised in the design process. The quality of this methodology is proven by the efficiency of the test vector suite used in the wafer and packaged tests. The same approach can also be used in the bitstream generation for FPGA application.

Automated test bitstream generation for an SOI-based FPGA

We present a novel programming circuit used in our radiation-hardened field programmable gate array (FPGA) chip. This circuit provides the ability to write user-defined configuration data into an FPGA and then read it back. The proposed circuit adopts the direct-access programming point scheme instead of the typical long token shift register chain. It not only saves area but also provides more flexible configuration operations. By configuring the proposed partial configuration control register, our smallest configuration section can be conveniently configured as a single data and a flexible partial configuration can be easily implemented. The hierarchical simulation scheme, optimization of the critical path and the elaborate layout plan make this circuit work well. Also, the radiation hardened by design programming point is introduced. This circuit has been implemented in a static random access memory (SRAM)-based FPGA fabricated by a 0.5 μm partial-depletion silicon-on-insulator CMOS process. The function test results of the fabricated chip indicate that this programming circuit successfully realizes the desired functions in the configuration and read-back. Moreover, the radiation test results indicate that the programming circuit has total dose tolerance of 1 × 105 rad(Si), dose rate survivability of 1.5 × 1011 rad(Si)/s and neutron fluence immunity of 1 × 1014 n/cm2.

http://iopscience.iop.org/article/10.1088/1674-4926/32/8/085012/pdf

Design and implementation of a programming circuit in radiation-hardened FPGA

This paper introduces a complete CAD toolset for the implementation of digital logic in a field-programmable gate array (FPGA) platform. Compared with existing academic toolsets, this toolset introduces formal verification in each step of the tool flow, especially the formal verification of the configuration bitstream. The FPGA CAD tool verification flow using Formality is presented in detail. Using plug-in technology, we have developed an integrated FPGA design kit to incorporate all tools together.

Stanley L. Chen

Papers

Microcontroller virtual memory system and method

A radiation-hardened SOI-based FPGA

Automated test bitstream generation for an SOI-based FPGA

Design and implementation of a programming circuit in radiation-hardened FPGA

The Design and Verification of FPGA CAD Toolset