High doses of fast neutrons is detrimental to the performance of most common solid-state devices such as diodes and transistors. The ionizing effect is observed in particular for diodes used as simple integrated temperature sensors, or thermodiodes, when their junction voltage is measured at constant current bias. In this work, we present a low-power and in situ mitigation technique based on Silicon-on-Insulator (SOI) microhotplates to recover thermodiodes. The basic operating principle consists in annealing the temperature-sensitive diodes integrated on the membrane during or after their irradiation in order to restore similar sensing characteristics over time. We measured thermodiodes integrated to microhotplates during their irradiation by fast neutrons (23 MeV peak) with total doses about 2.97±0.08 kGy. The membrane annealing is taking place at 450 °C using 40 mW of electrical power. Thanks to the annealing, the diode keeps a total measurement error below 0.5 °C. In this harsh radiation environment and beside the good tolerance of the thermodiodes and the membrane materials to the total ionizing dose, the thermodiode located on the heating membrane keeps a constant sensitivity. The demonstrated resistance of microhotplates and the integrated thermodiodes to fast neutron radiations can extend their use in nuclear plants and for radiation detectors.

A low-power and in situ annealing mitigation technique for fast neutrons irradiation of integrated temperature sensing diodes

The invention discloses a configuration method for detecting a wiring resource fault in a field programmable gate array. The method comprises the following steps of: configuration of switch wiring resources in an upper right direction and a left lower direction; configuration of switch wiring resources in an upper left direction and a right lower direction; and configuration of switch wiring resources in an upper lower direction and a left right direction, wherein the aforementioned steps all comprise configuration of common switch wiring resources and configuration of boundary switch wiring resources.

Configuration method for wiring resource fault detection

In order to minimize leakage current increase under total ionizing dose (TID) radiation in high density memory circuits, a new isolation technique, combining deep trench isolation (DTI) between the wells, local oxidation of silicon (LOCOS) isolation between the devices within the well, and a P-diffused area in order to limit leakage at the isolation edge is implemented in partly-depleted silicon-on-insulator (PD-SOI) technology. This radiation hardening technique can minimize the layout area by more than 60%, and allows flexible placement of the body contact. Radiation hardened transistors and 256 Kb flash memory chips are designed and fabricated in a 0.6 μm PD-SOI process. Experiments show that no obvious increase in leakage current is observed for single transistors under 1 Mrad(Si) radiation, and that the 256 Kb memory chip still functions well after a TID of 100 krad(Si), with only 50% increase of the active power consumption in read mode.

https://iopscience.iop.org/article/10.1088/1674-4926/35/2/024003/pdf

A PD-SOI based DTI-LOCOS combined cross isolation technique for minimizing TID radiation induced leakage in high density memory

For an SOI-FPGA (silicon-on-insulator field programmable gate arrays) (VS1000) fabricated with 0.5 μm SOI-CMOS (silicon-on-insulator complementary-metal-oxide-semiconductor) process, a complete integrated platform of FPGA computer-aided design (CAD) toolset (VDK) is developed, which can convert the Verilog HDL (hardware description language) description into a bitstream and finally download it into an FPGA. Experiments and testing verify that this FPGA CAD works well and efficiently.

An Integrated Framework of CAD Tool for an SOI-Based FPGA

Design and implementation of an integrated multi-level FPGA design system: Design and implementation of an integrated multi-level FPGA design system

A radiation-hardened SRAM-based field programmable gate array VS1000 is designed and fabricated with a 0.5 m partial-depletion silicon-on-insulator logic process at the CETC 58th Institute. The new logic cell (LC), with a multi-mode based on 3-input look-up-table (LUT), increases logic density about 12% compared to a traditional 4-input LUT. The logic block (LB), consisting of 2 LCs, can be used in two functional modes: LUT mode and distributed read access memory mode. The hierarchical routing channel block and switch block can significantly improve the flexibility and routability of the routing resource. The VS1000 uses a CQFP208 package and contains 392 reconfigurable LCs, 112 reconfigurable user I/Os and IEEE 1149.1 compatible with boundary- scan logic for testing and programming. The function test results indicate that the hardware and software cooperate successfully and the VS1000 works correctly. Moreover, the radiation test results indicate that the VS1000 chip has total dose tolerance of 100 krad(Si), a dose rate survivability of 1.5 10 11 rad(Si)/s and a neutron fluence immunity of 1 10 14 n/cm 2 .

https://iopscience.iop.org/article/10.1088/1674-4926/32/7/075012/pdf

A radiation-hardened SOI-based FPGA

We present an input/output block (IOB) array used in the radiation-hardened SRAM-based field- programmable gate array (FPGA) VS1000, which is designed and fabricated with a 0.5 m partially depleted silicon-on-insulator (SOI) logic process at the CETC 58th Institute. Corresponding with the characteristics of the FPGA, each IOB includes a local routing pool and two IO cells composed of a signal path circuit, configurable input/output buffers and an ESD protection network. A boundary-scan path circuit can be used between the pro- grammable buffers and the input/output circuit or as a transparent circuit when the IOB is applied in different modes. Programmable IO buffers can be used at TTL/CMOS standard levels. The local routing pool enhances the flexibility and routability of the connection between the IOB array and the core logic. Radiation-hardened designs, including A-type and H-type body-tied transistors and special D-type registers, improve the anti-radiation performance. The ESD protection network, which provides a high-impulse discharge path on a pad, prevents the breakdown of the core logic caused by the immense current. These design strategies facilitate the design of FPGAs with different ca- pacities or architectures to form a series of FPGAs. The functionality and performance of the IOB array is proved after a functional test. The radiation test indicates that the proposed VS1000 chip with an IOB array has a total dose tolerance of 100 krad(Si), a dose survivability rate of 1.5 10 11 rad(Si)/s, and a neutron fluence immunity of 1 10 14 n/cm 2 .

https://iopscience.iop.org/article/10.1088/1674-4926/33/1/015010/pdf

Wang Jian

Papers

A radiation-hardened SOI-based FPGA

An IO block array in a radiation-hardened SOI SRAM-based FPGA