With the increasing popularity of the Internet of Things and massive Machine Type Communication technologies, the number of connected devices is rising. However, although enabling valuable effects to our lives, bandwidth and latency constraints challenge Cloud processing of their associated data amounts. A promising solution to these challenges is the combination of Edge and approximate computing techniques that allows for data processing nearer to the user. This article aims to survey the potential benefits of these paradigms’ intersection. We provide a state-of-the-art review of circuit-level and architecture-level hardware techniques and popular applications. We also outline essential future research directions.

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Approximation Opportunities in Edge Computing Hardware: A Systematic Literature Review

This paper proposes a novel approach suitable to design energy-efficient approximate multipliers using both ASIC and FPGAs. The new strategy harnesses specific encoding logics based on bit significance and computes the approximate product performing accurate sub-multiplications by applying an unconventional approach instead of using approximate computational modules implementing traditional static or dynamic bit-truncation approaches. The proposed platform-independent architecture exhibits an energy saving of up to 80% over the accurate counterparts and significantly better behavior in terms of accuracy loss with respect to competitor approximate architectures. When employed in 2D digital filters and edge detectors, the novel approximate multipliers lead to an energy consumption up to ~82% lower than the accurate counterparts, which is up to ~2 times higher than that obtained by state-of-the-art competitors.

https://www.mdpi.com/2079-9268/12/4/49/pdf?version=1664254066

Designing Energy-Efficient Approximate Multipliers

Co‐design implementation of High Efficiency Video Coding standard encoder on Zynq MPSoC

High Efficiency Video Coding (HEVC) is the latest video standard developed by the Joint Video Exploration Team. HEVC is able to offer better compression results than preceding standards but it suffers from a high computational complexity. In particular, one of the most time consuming blocks in HEVC is the fractional-sample interpolation filter, which is used in both the encoding and the decoding processes. Integrating different state-of-the-art techniques, this paper presents an architecture for interpolation filters, able to trade quality for energy and power efficiency by exploiting approximate interpolation filters and by halving the amount of required memory with respect to state-of-the-art implementations.

https://www.mdpi.com/2079-9268/10/3/24/pdf

Stefania Preatto

Papers

Optimized VLSI Architecture of HEVC Fractional Pixel Interpolators with Approximate Computing