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TL;DR: Several very large scale integration (VLSI) architectures suitable for turbo decoder implementation are proposed and compared in terms of complexity and performance; the impact on the VLSI complexity of system parameters like the state number, number of iterations, and code rate are evaluated for the different solutions.

TL;DR: This work presents a novel formulation of the decoding algorithm that strongly simplifies internal communication requirements and enables the development of decoders supporting generally defined LDPC codes, and the resulting architecture is tailored to decode both IEEE 802.11n and IEEE802.16eLDPC codes.

TL;DR: This work aims at providing an up-to-date survey, especially covering the prominent works from the last 3 years of the hardware architectures research for DNNs, covering the latest techniques in the field of dataflow, reconfigurability, variable bit-width, and sparsity.

TL;DR: This work summarizes and compares the works for four leading platforms for the execution of algorithms such as CPU, GPU, FPGA and ASIC describing the main solutions of the state-of-the-art, giving much prominence to the last two solutions since they offer greater design flexibility and bear the potential of high energy-efficiency, especially for the inference process.

TL;DR: The hardware architectures of typical IoT devices are presented and many of the low power techniques which make them appealing for a large scale of applications are summed up.