IEEE transactions on computer-aided design of integrated circuits and systems : a publication of the IEEE Circuits and Systems Society

VLSI Test Principles and Architectures: Design for Testability (Systems on Silicon)

Advances in semiconductor process and design technology enable the design of complex system chips. Traditional IC design in which every circuit is designed from scratch and reuse is limited to standard-cell libraries, is more and more replaced by a design style based on embedding large reusable modules, the so-called cores. This core-based design poses a series of new challenges, especially in the domains of manufacturing test and design validation and debug. This paper provides an overview of current industrial practices as well as academic research in these areas. We also discuss industry-wide efforts by VSIA and IEEE P1500 and describe the challenges for future research.

Testing embedded-core based system chips

A multi-media interface (12) is disclosed for interfacing multi-media voice and data between a host messaging center (14) and various communication networks (8) including, for example, the public switched telephone network (PSTN), the packet switched public data network (PSPDN), and the cellular telephone and paging networks at a very high data throughput. The multi-media interface (12) provides protocol conversions for different telecommunication protocols corresponding to various types of telecommunications media, for example, speech in analog form, speech data in pulsed code modulated (PCM) form, modem data in PCM form, data in analog form modulating sinusoidal carriers, and data in various digital forms associated with a variety of protocol standards.

Multi-media interface

Recently, designers have been embedding reusable modules to build on-chip systems that form rich libraries of predesigned, preverified building blocks. These embedded cores make it easier to import technology to a new system and differentiate the corresponding product by leveraging intellectual property advantages. Most importantly, design reuse shortens the time-to-market for new systems. The attributes that make system chips built with embedded IP cores an attractive methodology-design reuse, heterogeneity, reconfigurability, and customizability-also make testing and debugging these chips a complex challenge. The authors review the various alternatives for testing embedded cores and describe solutions and proposed standards that are expected to play a key role in developing the core based design paradigm.

Testing embedded-core-based system chips

An accurate and simple method is introduced for determining the third order polynomial that best fits a set of data points containing random noise. The coefficients of the polynomial are translated into offset, gain, and harmonic distortion for an analog-to-digital converter (ADC) driven by a digital-to-analog converter (DAC) or other appropriate signal source. The algorithm is efficient enough to be implemented as a built-in self-test for an IC, and is particularly suitable for sigma-delta converters.

A simplified polynomial-fitting algorithm for DAC and ADC BIST

Phase-locked loops (PLLs) are an essential building block of most digital and mixed-signal ICs. This paper describes a built-in self-test (BIST) circuit that tests the key analog parameters of PLLs, using only logic gates that can be synthesized from a hardware description language (HDL). The parameters tested include lock range, lock time, RMS jitter, and loop gain (from which the natural frequency is calculated). Experimental waveforms and results are shown for a 200 MHz PLL which uses a phase-frequency detector. Test time is typically 10 ms, much faster than for conventional testing.

BIST for phase-locked loops in digital applications

In methods and apparatus for testing a digital system, scannable memory elements of the digital system are configured in a scan mode in which the memory elements are connected to define a plurality of scan chains. A test stimulus pattern is clocked into each of the scan chains at a respective clock rate, at least two of the clock rates being different from one another. The memory elements of each scan chain are then configured in a normal operation mode in which the memory elements are interconnected by the combinational network for at least one clock cycle at a highest of the respective clock rates. The memory elements are then reconfigured in the scan mode, and a test response pattern is clocked out of each of the scan chains at its respective clock rate. The methods and apparatus are particularly useful for testing digital systems such as digital integrated circuits in which different memory elements are clocked at different rates during normal operation.

Multiple clock rate test apparatus for testing digital systems

This paper first summarizes the complete range of analog defects and resultant faults. A complete set of metrics is then derived for measuring the quality of analog tests. The probability-based equations for fault coverage, defect level, yield coverage, and yield loss are self-consistent, and consistent with existing equations for digital test metrics. We introduce the concept of partial coverage, show that it is inherent to analog testing, and show that coverage cannot be calculated without knowing the performance specifications for a circuit, as well as the process parameter distributions. Practical methods for calculating probabilities are discussed, and simple, illustrative examples given.

Test metrics for analog parametric faults

One of the challenges of testing at multiGbps rates is jitter characterization. We introduce a new technique that allows for attaining on-chip measurements at a substantial level of accuracy. We propose new algorithms that allow a wide frequency range, supporting the desired accuracy while guaranteeing signal integrity and low overhead. One advantage of this approach is that we can reliably simulate it with a logic simulator, and the results at one frequency are indicative of the results at any frequency.

Stephen Sunter

Papers

A simplified polynomial-fitting algorithm for DAC and ADC BIST

BIST for phase-locked loops in digital applications

Multiple clock rate test apparatus for testing digital systems

Test metrics for analog parametric faults

On-chip digital jitter measurement, from megahertz to gigahertz