LogicVision

About: LogicVision is a based out in . It is known for research contribution in the topics: Fault coverage & Automatic test pattern generation. The organization has 56 authors who have published 116 publications receiving 4799 citations.

Testing embedded-core based system chips

Abstract: Advances in semiconductor process and design technology enable the design of complex system chips. Traditional IC design in which every circuit is designed from scratch and reuse is limited to standard-cell libraries, is more and more replaced by a design style based on embedding large reusable modules, the so-called cores. This core-based design poses a series of new challenges, especially in the domains of manufacturing test and design validation and debug. This paper provides an overview of current industrial practices as well as academic research in these areas. We also discuss industry-wide efforts by VSIA and IEEE P1500 and describe the challenges for future research.

Testing embedded-core-based system chips

Abstract: Recently, designers have been embedding reusable modules to build on-chip systems that form rich libraries of predesigned, preverified building blocks. These embedded cores make it easier to import technology to a new system and differentiate the corresponding product by leveraging intellectual property advantages. Most importantly, design reuse shortens the time-to-market for new systems. The attributes that make system chips built with embedded IP cores an attractive methodology-design reuse, heterogeneity, reconfigurability, and customizability-also make testing and debugging these chips a complex challenge. The authors review the various alternatives for testing embedded cores and describe solutions and proposed standards that are expected to play a key role in developing the core based design paradigm.

On-Line Testing for VLSI—A Compendium of Approaches

Abstract: This paper presents an overview of a comprehensive collection of on-line testing techniques for VLSI. Such techniques are for instance: self-checking design, allowing high quality concurrent checking by means of hardware cost drastically lower than duplication; signature monitoring, allowing low cost concurrent error detection for FSMs; on-line monitoring of reliability relevant parameters such as current, temperature, abnormal delay, signal activity during steady state, radiation dose, clock waveforms, etc.; exploitation of standard BIST, or implementation of BIST techniques specific to on-line testing (Transparent BIST, Built-In Concurrent Self-Test,...); exploitation of scan paths to transfer internal states for performing various tasks for on-line testing or fault tolerance; fail-safe techniques for VLSI, avoiding complex fail-safe interfaces using discrete components; radiation hardened designs, avoiding expensive fabrication process such as SOI, etc.

Test requirements for embedded core-based systems and IEEE P1500

Abstract: Chips comprising reusable cores, i.e. pre-designed Intellectual Property (IP) blocks, have become an important part of IC-based system design. Using embedded cores enables the design of high-complexity system-chips with densities as high as millions of gates on a single die. The increase in using pre-designed IP cores in system-chips adds to the complexity of test. To test system-chips adequately, test solutions need to be incorporated into individual cores and then the tests from individual cores need to be scheduled and assembled into a chip level test. However with the increased usage of cores from multiple and diverse sources, it is essential to create standard mechanisms to make core test plug-and-play possible. This paper discusses in general the challenges in testing core-based system-chips and describes their corresponding test solutions. It concentrates on the common test requirements and introduces the on-going standardization efforts, specifically under IEEE P1500 Working Group, which is meant to standardize the interface between a core test and its host the System-on-Chip.

Towards a standard for embedded core test: an example

Abstract: Integrated circuits are increasingly designed by embedding pre-designed reusable cores. IEEE P1500 Standard for Embedded Core Test (SECT) is a standard-under-development that aims at improving ease of reuse and facilitating interoperability with respect to the test of such core-based ICs, especially if they contain cores from different sources. This paper briefly describes IEEE P1500, and illustrates through a simplified example its dual compliance concept, its Scalable Hardware Architecture, and its Core Test Language. This paper provides a preliminary, unapproved view on IEEE P1500. The standard is still under development, and this paper only reflects the view of five active participants of the Standardization Committee on its current status.