There is, I think, something ethereal about i —the square root of minus one. I remember first hearing about it at school. It seemed an odd beast at that time—an intruder hovering on the edge of reality.

Usually familiarity dulls this sense of the bizarre, but in the case of i it was the reverse: over the years the sense of its surreal nature intensified. It seemed that it was impossible to write mathematics that described the real world in …

I and i

An object is to provide a semiconductor device of which a manufacturing process is not complicated and by which cost can be suppressed, by forming a thin film transistor using an oxide semiconductor film typified by zinc oxide, and a manufacturing method thereof. For the semiconductor device, a gate electrode is formed over a substrate; a gate insulating film is formed covering the gate electrode; an oxide semiconductor film is formed over the gate insulating film; and a first conductive film and a second conductive film are formed over the oxide semiconductor film. The oxide semiconductor film has at least a crystallized region in a channel region.

Semiconductor device, and manufacturing method thereof

This paper presents the current state of understanding of the factors that limit the continued scaling of Si complementary metal-oxide-semiconductor (CMOS) technology and provides an analysis of the ways in which application-related considerations enter into the determination of these limits. The physical origins of these limits are primarily in the tunneling currents, which leak through the various barriers in a MOS field-effect transistor (MOSFET) when it becomes very small, and in the thermally generated subthreshold currents. The dependence of these leakages on MOSFET geometry and structure is discussed along with design criteria for minimizing short-channel effects and other issues related to scaling. Scaling limits due to these leakage currents arise from application constraints related to power consumption and circuit functionality. We describe how these constraints work out for some of the most important application classes: dynamic random access memory (DRAM), static random access memory (SRAM), low-power portable devices, and moderate and high-performance CMOS logic. As a summary, we provide a table of our estimates of the scaling limits for various applications and device types. The end result is that there is no single end point for scaling, but that instead there are many end points, each optimally adapted to its particular applications.

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Device scaling limits of Si MOSFETs and their application dependencies

A very high density field programmable memory is disclosed. An array is formed vertically above a substrate using several layers, each layer of which includes vertically fabricated memory cells. The cell in an N level array may be formed with N+1 masking steps plus masking steps needed for contacts. Maximum use of self alignment techniques minimizes photolithographic limitations. In one embodiment the peripheral circuits are formed in a silicon substrate and an N level array is fabricated above the substrate.

Vertically-stacked, field-programmable, nonvolatile memory and method of fabrication

A Three Dimensional Structure (3DS) Memory (100) allows for physical separation of the memory circuits (103) and the control logic circuit (101) onto different layers (103) such that each layer may be separately optimized. One control logic circuit (101) suffices for several memory circuits (103), reducing cost. Fabrication of 3DS memory (100) involves thinning of the memory circuit (103) to less than 50 microns in thickness and bonding the circuit to a circuit stack while still in wafer substrate form. Fine-grain high density inter-layer vertical bus connections (105) are used. The 3DS memory (100) manufacturing method enables several performance and physical size efficiencies, and is implemented with established semiconductor processing techniques.

Three dimensional structure memory

Three-dimensional ESD structures are constructed in SOI technology that utilize both bulk devices and thin film SOI devices.

3-D CMOS-on-SOI ESD structure and method

The invention comprises a diode in a well having trench isolation that has an edge. Both the well contact of the diode and the rectifying contact of the diode are silicided, but the silicide on the rectifying contact is spaced from the trench isolation edge. The spacing is provided by a gate stack or other mask. In one embodiment, the gate stack alone spaces the two diode contacts from each other, eliminating the need for trench isolation therebetween. The structure reduces diode series resistance and silicide junction penetration. It significantly improves heat flow in trench isolation technologies, increasing the level of ESD protection. The invention also comprises an SOI diode having a lightly doped region in the thin layer of semiconductor under a gate stack with an ohmic contact to the lightly doped region self-aligned to an edge of the gate stack.

Semiconductor diode with silicide films and trench isolation

About the Author. Preface. Acknowledgments. Chapter 1: Electrostatic Discharge. 1.1 Electricity and Electrostatics Discharge. 1.2 Fundamental Concepts of ESD Design. 1.3 Time Constants. 1.4 Capacitance, Resistance and Inductance and ESD. 1.5 Rules of Thumb and ESD. 1.6 Lumped versus Distributed Analysis and ESD. 1.7 ESD Metrics and Figures of Merit. 1.8 Twelve Steps to Building an ESD Strategy. 1.9 Summary and Closing Comments. Problems. References. Chapter 2: Design Synthesis. 2.1 Synthesis and Architecture of a Semiconductor Chip for ESD Protection. 2.2 Electrical and Spatial Connectivity. 2.3 ESD, Latchup, and Noise. 2.4 Interface Circuits and ESD Elements. 2.5 ESD Power Clamps Networks. 2.6 ESD Rail-to-Rail Devices. 2.7 Guard Rings. 2.8 Pads, Floating Pads, and No Connect Pads. 2.9 Structures Under Bond Pads. 2.10 Summary and Closing Comments. Problems. References. Chapter 3: Electrostatic Discharge (ESD) Design: MOSFET Design. 3.1 Basic ESD Design Concepts. 3.2 ESD MOSFET Design: Channel Width. 3.3 ESD MOSFET Design: Contact. 3.4 ESD MOSFET Design: Metal Distribution. 3.5 ESD MOSFET Design: Silicide Masking. 3.6 ESD MOSFET Design: Series Cascode Configurations. 3.7 ESD MOSFET Design: Multi-Finger Design Integration of Coupling and Ballasting Techniques. 3.8 ESD MOSFET Design: Enclosed Drain Design Practice. 3.9 ESD MOSFET Interconnect Ballasting Design. 3.10 ESD MOSFET Design: Source and Drain Segmentation. 3.11 Summary and Closing Comments. Problems. References. Chapter 4: Electrostatic Discharge (ESD) Design: Diode Design. 4.1 ESD Diode Design: ESD Basic. 4.2 ESD Diode Design: Anode. 4.3 ESD Diode Design: Interconnect Wiring. 4.4 ESD Diode Design: Polysilicon-Bound Diode Designs. 4.5 ESD Diode Design: n-Well Diode Design. 4.6 ESD Diode Design: np/p Substrate Diode Design. 4.7 ESD Diode Design: Diode String. 4.8 ESD Diode Design: Triple-Well Diodes. 4.9 ESD Design: BiCMOS ESD Design. 4.10 Summary and Closing Comments. Problems. References. Chapter 5: Silicon on Insulator (SOI) ESD Design. 5.1 SOI ESD Basic Concepts. 5.2 SOI ESD Design: MOSFET with Body Contact (T-Shaped Layout). 5.3 SOI ESD Design: SOI Lateral Diode Structure. 5.4 SOI ESD Design: Buried Resistors (BR) Elements. 5.5 SOI ESD Design: SOI Dynamic Threshold MOSFET (DTMOS). 5.6 SOI ESD Design: Dual-Gate (DG) MOSFETs. 5.7 SOI ESD Design: FinFET Structure. 5.8 SOI ESD Design: Structures in the Bulk Substrate. 5.9 SOI ESD Design: SOI-To-Bulk Contact Structures. 5.10 Summary and Closing Comments. Problems. References. Chapter 6: Off-Chip Drivers (OCD) and ESD. 6.1 Off-Chip Drivers (OCD). 6.2 Off-Chip Drivers: Mixed-Voltage Interface. 6.3 Off-Chip Drivers Self-Bias Well OCD Networks. 6.4 Off-Chip Drivers: Programmable Impedance (PIMP) OCD Networks. 6.5 Off-Chip Drivers: Universal OCDs. 6.6 Off-Chip Drivers: Gate-Array OCD Design. 6.7 Off-Chip Drivers: Gate Modulated Networks. 6.8 Off-Chip Driver ESD Design: Integration of Coupling and Ballasting Techniques. 6.9 Off-Chip Driver ESD Design: Substrate-Modulated Resistor-Ballasted MOSFET. 6.10 Summary and Closing Comments. Problems. References. Chapter 7: Receiver Circuits and ESD. 7.1 Receivers and ESD. 7.2 Receivers and ESD. 7.3 Receivers and Receiver Evolution. 7.4 Receiver Circuits with Pseudo-Zero VT Half-Pass Transmission Gates. 7.5 Receiver Circuits with Zero Transmission Gate. 7.6 Receiver Circuits with Bleed Transistors. 7.7 Receiver Circuits with Test Functions. 7.8 Receiver With Schmitt Trigger Feedback Networks. 7.9 Bipolar Transistor Receivers. 7.10 Summary and Closing Comments. Problems. References. Chapter 8: SOI ESD Circuits and Design Integration. 8.1 SOI ESD Design Integration. 8.2 SOI ESD Design: Diode Design. 8.3 SOI ESD Diode Design: Mixed Voltage Interface (MVI) Environments. 8.4 SOI ESD Networks in SOI CPU with Aluminum (Al) Interconnects. 8.5 SOI ESD Design in Copper (Cu) Interconnects. 8.6 SOI ESD Design with Gate Circuitry. 8.7 SOI and Dynamic Threshold ESD Networks. 8.8 SOI Technology and Miscellaneous ESD Issues 8.9 Summary and Closing Comments. Problems. References. Chapter 9: ESD Power Clamps. 9.1 ESD Power Clamp Design Practices. 9.2 ESD Power Clamps: Diode-Based. 9.3 ESD Power Clamps: MOSFET-Based. 9.4 ESD Power Clamps: Bipolar-Based. 9.5 ESD Power Clamps: Silicon Controlled Rectifier-Based. 9.6 Summary and Closing Comments. Problems. References. Index.

ESD: Circuits and Devices

Multichip semiconductor structures with consolidated circuitry are disclosed, along with programmable electrostatic discharge (ESD) protection circuits for chip input/output (I/O) nodes. The multichip structures include a first semiconductor chip having a first circuit at least partially providing a first predetermined circuit function, and a second semiconductor chip electrically and mechanically coupled to the first semiconductor chip. The second semiconductor device chip has a second circuit that at least partially provides a circuit function to the first circuit of the first semiconductor chip. In one embodiment, the first semiconductor chip comprises a memory array chip, while the second semiconductor chip comprises a logic chip wherein at least some peripheral circuitry necessary for accessing the memory array of the memory array chip resides within the logic chip. This allows the removal of redundant circuitry from identical chips of a multichip structure. Also disclosed is removing, adding or balancing ESD circuit loading on input/output nodes of a multichip stack. Various techniques are presented for selective removal of ESD circuitry from commonly connected I/O nodes. Any circuitry interfacing with an external device may be rebalanced at the multichip level using this concept.

Multichip semiconductor structures with consolidated circuitry and programmable ESD protection for input/output nodes

A fabrication method and resultant monolithic electronic module comprising a plurality of stacked planar extending arrays of integrated circuit chips. The fabrication method includes dicing a wafer of integrated circuit chips into a plurality of arrays of integrated circuit chips. The arrays of integrated circuit chips are then stacked to form an electronic module. A metallization pattern may be deposited on a substantially planar surface of the electronic module, and used to interconnect the various arrays of integrated circuit chips contained therein. Specific details of the fabrication method and resultant multi-chip package are set forth.

Steven H. Voldman

Papers

3-D CMOS-on-SOI ESD structure and method

Semiconductor diode with silicide films and trench isolation

ESD: Circuits and Devices

Multichip semiconductor structures with consolidated circuitry and programmable ESD protection for input/output nodes

Method for forming a monolithic electronic module by dicing wafer stacks