In this paper, the state of the art in ultra-low power (ULP) VLSI design is presented within a unitary framework for the first time. A few general principles are first introduced to gain an insight into the design issues and the approaches that are specific to ULP systems, as well as to better understand the challenges that have to be faced in the foreseeable future. Intuitive understanding is accompanied by rigorous analysis for each key concept. The analysis ranges from the circuit to the micro-architectural level, and reference is given to process, physical and system levels when necessary. Among the main goals of this paper, it is shown that many paradigms and approaches borrowed from traditional above-threshold low-power VLSI design are actually incorrect. Accordingly, common misconceptions in the ULP domain are debunked and replaced with technically sound explanations.

Ultra-Low Power VLSI Circuit Design Demystified and Explained: A Tutorial

Sensing systems such as biomedical implants, infrastructure monitoring systems, and military surveillance units are constrained to consume only picowatts to nanowatts in standby and active mode, respectively. This tight power budget places ultra-low power demands on all building blocks in the systems. This work proposes a voltage reference for use in such ultra-low power systems, referred to as the 2T voltage reference, which has been demonstrated in silicon across three CMOS technologies. Prototype chips in 0.13 μm show a temperature coefficient of 16.9 ppm/°C (best) and line sensitivity of 0.033%/V, while consuming 2.22 pW in 1350 μm2. The lowest functional Vdd 0.5 V. The proposed design improves energy efficiency by 2 to 3 orders of magnitude while exhibiting better line sensitivity and temperature coefficient in less area, compared to other nanowatt voltage references. For process spread analysis, 49 dies are measured across two runs, showing the design exhibits comparable spreads in TC and output voltage to existing voltage references in the literature. Digital trimming is demonstrated, and assisted one temperature point digital trimming, guided by initial samples with two temperature point trimming, enables TC <; 50 ppm/°C and ±0.35% output precision across all 25 dies. Ease of technology portability is demonstrated with silicon measurement results in 65 nm, 0.13 μm, and 0.18 μm CMOS technologies.

A Portable 2-Transistor Picowatt Temperature-Compensated Voltage Reference Operating at 0.5 V

Circuit blocks for a 1.5 mm3 microsystem enable continuous monitoring of intraocular pressure. Due to power and form-factor limitations, circuit blocks are designed at nanowatt power levels not completely explored before. The system includes a 75% efficient 90 nW DC-DC converter which is the most efficient reported sub- μW converter in literature. It also includes a novel 4.7 nJ/bit FSK radio that achieves 10 cm of transmission range at 10 -6 BER which is also the lowest number reported for short-range through-tissue wireless links for biomedical implants. A MEMS capacitive sensor and ΣΔ capacitance-to-digital converter measure IOP with 0.5 mmHg accuracy. A microcontroller processes and saves IOP data and stores it in a 2.4 fW/bitcell SRAM. The microsystem harvests a maximum power of 80 nW in sunlight with a light irradiance of 100 mW/cm2 AM 1.5 from an integrated 0.07 mm2 solar cell to recharge a 1 mm2 1 μAh thin-film battery and power the load circuits. The design achieves zero-net-energy operation with 1.5 hours of sunlight or 10 hours of bright indoor lighting daily.

Circuits for a Cubic-Millimeter Energy-Autonomous Wireless Intraocular Pressure Monitor

Glaucoma is the leading cause of blindness, affecting 67 million people worldwide. The disease damages the optic nerve due to elevated intraocular pressure (IOP) and can cause complete vision loss if untreated. IOP is commonly assessed using a single tonometric measurement, which provides a limited view since IOP fluctuates with circadian rhythms and physical activity. Continuous measurement can be achieved with an implanted monitor to improve treatment regiments, assess patient compliance to medication schedules, and prevent unnecessary vision loss. The most suitable implantation location is the anterior chamber of the eye, which is surgically accessible and out of the field of vision. The desired IOP monitor (IOPM) volume is limited to 1.5mm3 (0.5x1.5x2mm3) by the size of a self-healing incision, curvature of the cornea, and dilation of the pupil.

/pdf/a-cubic-millimeter-energy-autonomous-wireless-intraocular-41yy5aye21.pdf

A cubic-millimeter energy-autonomous wireless intraocular pressure monitor

In wireless environments, transmission and reception costs dominate system power consumption, motivating research effort on new technologies capable of reducing the footprint of the radio, paving the way for the Internet of Things. The most important challenge is to reduce power consumption when receivers are idle, the so called idle-listening cost. One approach proposes switching off the main receiver, then introduces new wake-up circuitry capable of detecting an incoming transmission, optionally discriminating the packet destination using addressing, then switching on the main radio only when required. This wake-up receiver technology represents the ultimate frontier in low power radio communication. In this paper, we present a comprehensive literature review of the research progress in wake-up radio (WuR) hardware and relevant networking software. First, we present an overview of the WuR system architecture, including challenges to hardware design and a comparison of solutions presented throughout the last decade. Next, we present various medium access control and routing protocols as well as diverse ways to exploit WuRs, both as an extension of pre-existing systems and as a new concept to manage low-power networking.

/pdf/ultra-low-power-wake-up-radios-a-hardware-and-networking-55kvi6zf2s.pdf

Ultra Low Power Wake-Up Radios: A Hardware and Networking Survey

This brief presents a fast energy-efficient level converter capable of converting an input signal from subthreshold voltages up to the nominal supply voltage. Measured results from a 130-nm test chip show robust conversion from 188 mV to 1.2 V with no intermediate supplies required. A combination of circuit methods makes the converter robust to the large variations in the current characteristics of subthreshold circuits. To support dynamic voltage scaling, the level converter can upconvert an input at any voltage within this range to 1.2 V.

An Energy-Efficient Subthreshold Level Converter in 130-nm CMOS

This paper describes a 0.13-µm CMOS sub-threshold (sub-V T ) mixed-signal system-on-chip (SoC) that acquires and processes an electrocardiogram (ECG) signal for wireless ECG monitoring. The SoC uses a sub-threshold digital microcontroller (μC) for adaptive control of the sub-V T biased analog components and for processing the ECG data. The μC operates from 0.24 V to 1.2 V and consumes as little as 1.51 pJ per instruction. The SoC consumes only 2.6 µW while providing either heart rate or ECG data.

A 2.6-µW sub-threshold mixed-signal ECG SoC

Batteryless operation and ultra-low-power (ULP) wireless communication will be two key enabling technologies as the IC industry races to keep pace with the IoE projections of 1T-connected sensors by 2025. Bluetooth Low-Energy (BLE) is used in many consumer IoE devices now because it offers the lowest average power for a radio that can communicate directly to a mobile device [1]. The BLE standard requires that the IoE device continuously advertises, which initiates the connection to a mobile device. Sub-1s advertisement intervals are common to minimize latency. However, this continuous advertising results in a typical minimum average power of 10's of µW at low duty-cycles. This leads to the quoted 1-year lifetimes of event-driven IoE devices (e.g. tracking tags, ibeacons) that operate from coin-cell batteries. This minimum power is too high for robust, batteryless operation in a small form-factor.

26.8 A 236nW −56.5dBm-sensitivity bluetooth low-energy wakeup receiver with energy harvesting in 65nm CMOS

On-chip circuit aging sources, like negative bias temperature instability (NBTI), hot-carrier injection (HCI), electromigration, and oxide breakdown, are reducing expected chip lifetimes. Being able to track the actual aging process is one way to avoid unnecessarily large design margins. This work proposes a sensing scheme that uses sets of reliability sensors capable of accurately tracking NBTI PMOS current degradations across process, temperature, and varying activity factors. We show that a set of 1000 such small sensors can predict chip lifetime to an uncertainty of 7% to 10%. We also show that, once the total area dedicated to sensing is chosen, the lifetime prediction uncertainty is almost insensitive to the tradeoff between the number of sensors and the area of each individual sensor.

Small embeddable NBTI sensors (SENS) for tracking on-chip performance decay

NBTI has been a major aging mechanism for advanced CMOS technology and PBTI is also looming as a big concern. This work first proposes a compact on-chip sensor design that tracks both NBTI and PBTI for both logic and SRAM circuits. Embedded in an SRAM array the sensor takes the form of a 6T SRAM cell and is at least 30× smaller than previous designs. Extensively reusing the SRAM peripheral circuitry minimizes control logic overhead. Sensing overhead is further amortized as the sensors can be both reconfigured and recycled as functional SRAM cells, potentially increasing SRAM yield when other bit cells fail due to initial process variation or long time aging effects. The paper also proposes a variation-aware sensor system design methodology by quantifying and leveraging the tradeoff between the size and number of sensors and the system sensing precision. Design examples show that a system of 500 sensors can achieve 4mV precision with 98.8% confidence, and a system of 1K sensors designed for 1M SRAM bit cells achieves 2000× area overhead reduction compared to a worst-case based approach.

Stuart N. Wooters

Papers

An Energy-Efficient Subthreshold Level Converter in 130-nm CMOS

A 2.6-µW sub-threshold mixed-signal ECG SoC

26.8 A 236nW −56.5dBm-sensitivity bluetooth low-energy wakeup receiver with energy harvesting in 65nm CMOS

Small embeddable NBTI sensors (SENS) for tracking on-chip performance decay

SRAM-based NBTI/PBTI sensor system design