Showing papers in "IEEE Transactions on Circuits and Systems Ii-express Briefs in 2010"

A Study of Loosely Coupled Coils for Wireless Power Transfer

Abstract: Nonradiative wireless power transfer using magnetically coupled coils is studied in order to transfer a predetermined amount of power at the maximum efficiency. Accordingly, a conceptual wireless power transfer system and a tuning method are presented. Such a study is essential for effectively exploiting the inherent ability of a given pair of coupled coils. With the equations for inductance and resistance calculations, the system performance is evaluated and verified with well-known experimental results and circuit simulations.

Full Passive UHF Tag With a Temperature Sensor Suitable for Human Body Temperature Monitoring

Abstract: A long-range UHF RF identification (RFID) sensor has been designed using a 0.35- ?m CMOS standard process. The power-optimized tag, combined with the ultralow-power temperature sensor, allows an ID and a temperature reading range of 2 m from a 2-W effective radiated power output power reader. The temperature sensor is based on a ring oscillator, where the temperature dependence of the oscillation frequency is used for thermal sensing. The temperature sensor exhibits a resolution of 0.035°C and an inaccuracy value lower than 0.1°C in the range from 35°C to 45°C after two-point calibration. The average power consumption of the temperature sensor is only 110 nW at ten conversions per second while keeping a high resolution and accuracy. These properties allow the use of the RFID as a batteryless sensor in a wireless human body temperature monitoring system.

Fractional-Order Memristor-Based Chua's Circuit

Abstract: This express brief deals with the memristor-based Chua's circuit. For the first time, the fractional-order model for such system is presented. A numerical solution of the fractional-order memristor-based Chua's equations is derived for simulations. The dynamical behavior and stability analysis of this system are described and investigated as well.

Predictive Controller Design of Networked Systems With Communication Delays and Data Loss

Abstract: This brief studies the predictive controller design of networked systems with communication delay and data loss. A networked predictive control scheme is employed to compensate for communication delay and data loss actively rather than passively. Based on analysis of the closed-loop networked predictive control systems, a design strategy of the predictive controller is proposed. The designed predictive controller can achieve the desired control performance and also guarantee the system stability. A numerical example demonstrates the compensation for communication delay and data loss in networked systems using the proposed predictive controller design strategy.

A Brief Introduction to Time-to-Digital and Digital-to-Time Converters

Abstract: This paper presents a short review of time-to-digital and digital-to-time converters (TDCs and DTCs, respectively) adopting a time-mode signal-processing perspective. The primary definitions, operating principles, and basic building blocks are presented. The discussion applies to most, if not all, DTCs and TDCs. A series of voltage-controlled delay units are used as the primary building block of these converter circuits. When configured in a servo-loop manner, a very short time resolution is achievable with excellent manufacturing robustness. Such designs can be synthesized in field-programmable gate arrays (FPGAs) or constructed in custom silicon. TDCs and DTCs are not new, as they have extensively been used for making very accurate and repeatable time measurements in both the physics-related and semiconductor industry. Today, TDCs and DTCs are finding new applications in phase-locked loops and frequency synthesizers.

A Subthreshold to Above-Threshold Level Shifter Comprising a Wilson Current Mirror

Abstract: In this brief, we propose a novel level shifter circuit that is capable of converting subthreshold to above-threshold signal levels. In contrast to other existing implementations, it does not require a static current flow and can therefore offer considerable static power savings. The circuit has been optimized and simulated in a 90-nm process technology. It operates correctly across process corners for supply voltages from 100 mV to 1 V on the low-voltage side. At the target design voltage of 200 mV, the level shifter has a propagation delay of 18.4 ns and a static power dissipation of 6.6 nW. For a 1-MHz input signal, the total energy per transition is 93.9 fJ. Simulation results are compared to an existing subthreshold to above-threshold level shifter implementation from the paper of Chen et al.

An Efficient VLSI Architecture for Nonbinary LDPC Decoders

Abstract: Low-density parity-check (LDPC) codes constructed over the Galois field GF(q), which are also called nonbinary LDPC codes, are an extension of binary LDPC codes with significantly better performance. Although various kinds of low-complexity quasi-optimal iterative decoding algorithms have been proposed, the VLSI implementation of nonbinary LDPC decoders has rarely been discussed due to their hardware unfriendly properties. In this brief, an efficient selective computation algorithm, which totally avoids the sorting process, is proposed for Min-Max decoding. In addition, an efficient VLSI architecture for a nonbinary Min-Max decoder is presented. The synthesis results are given to demonstrate the efficiency of the proposed techniques.

An RFID-Based Closed-Loop Wireless Power Transmission System for Biomedical Applications

Abstract: This brief presents a standalone closed-loop wireless power transmission system that is built around a commercial off-the-shelf (COTS) radio-frequency identification (RFID) reader (TRF7960) operating at 13.56 MHz. It can be used for inductively powering implantable biomedical devices in a closed loop. Any changes in the distance and misalignment between transmitter and receiver coils in near-field wireless power transmission can cause a significant change in the received power, which can cause either a malfunction or excessive heat dissipation. RFID circuits are often used in an open loop. However, their back telemetry capability can be utilized to stabilize the received voltage on the implant. Our measurements showed that the delivered power to the transponder was maintained at 11.2 mW over a range of 0.5 to 2 cm, while the transmitter power consumption changed from 78 mW to 1.1 W. The closed-loop system can also oppose voltage variations as a result of sudden changes in the load current.

A Capacitor-Less CMOS Active Feedback Low-Dropout Regulator With Slew-Rate Enhancement for Portable On-Chip Application

Abstract: A low-dropout regulator for on-chip application with active feedback and a slew-rate enhancement circuit to minimize compensation capacitance and speed up transient response is presented in this brief. The idea has been modeled and experimentally verified in a standard 0.35-?m CMOS process. The total compensation capacitance is 7 pF. From experimental results, the implemented regulator can operate from a supply voltage of 1.8-4.5 V with a minimum dropout voltage of 0.2 V at a maximum 100-mA load and I Q of 20 ?A.

Event-Driven Data Acquisition and Digital Signal Processing—A Tutorial

Abstract: Event-driven analog-to-digital conversion and associated digital signal processing techniques are reviewed. Such techniques, still in the research stage, have the potential to significantly reduce the consumption of energy and bandwidth resources in several important applications.

A 2.4-GS/s FFT Processor for OFDM-Based WPAN Applications

Abstract: This brief presents a fast Fourier transform (FFT) processor that provides high throughput rate (T.R.) by applying the eight-data-path pipelined approach for wireless personal area network applications. The hardware costs, including the power consumption and area, increase due to multiple data paths and increased wordlength along stages. To resolve these issues, a novel simplification method to reduce the hardware cost in multiplication units of the multiple-path FFT approach is proposed. A multidata scaling scheme to reduce wordlengths while preserving the signal-to-quantization-noise ratio is also presented. Using UMC 90-nm 1P9M technology, a 2048-point FFT processor test chip has been designed, and its 128-point FFT kernel has been fabricated for ultrawideband (UWB) applications and also for verification. The 2048-point FFT processor can provide a T.R. of 2.4 GS/s at 300 MHz with a power consumption of 159 mW. Compared with the four-data-path approach, a power consumption saving of about 30% can be achieved under the same T.R. In addition, the 128-point FFT kernel test chip has a measured power consumption of 6.8 mW with a T.R. of 409.6 MS/s at 52 MHz to meet the UWB standard with a saving in power consumption of about 40%.

An Energy-Efficient Subthreshold Level Converter in 130-nm CMOS

Abstract: This brief presents a fast energy-efficient level converter capable of converting an input signal from subthreshold voltages up to the nominal supply voltage. Measured results from a 130-nm test chip show robust conversion from 188 mV to 1.2 V with no intermediate supplies required. A combination of circuit methods makes the converter robust to the large variations in the current characteristics of subthreshold circuits. To support dynamic voltage scaling, the level converter can upconvert an input at any voltage within this range to 1.2 V.

Simple Autonomous Chaotic Circuits

Abstract: Over the last several decades, numerous electronic circuits exhibiting chaos have been proposed. Nonautonomous circuits with as few as two physical components have been developed. However, the operation of such circuits has typically traded physical simplicity for analytic complexity, or vice versa. In this brief, we present two simple autonomous chaotic circuits using only op-amps and linear time-invariant passive components. Each circuit employs one op-amp as a comparator to provide signum nonlinearity. The chaotic behavior is robust, and the circuits offer simple analysis, while minimizing both physical and model component counts.

On-Chip Aging Sensor Circuits for Reliable Nanometer MOSFET Digital Circuits

Abstract: Accurate performance-degradation monitoring of nanometer MOSFET digital circuits is one of the most critical issues in adaptive design techniques for overcoming the performance degradation due to aging phenomena such as negative bias temperature instability (NBTI) and hot carrier injection (HCI). Therefore, this paper proposes new on-chip aging sensor circuits which deploy a threshold voltage detector for monitoring the performance degradation of an aged MOSFET. The new aging sensor circuits measure the threshold voltage difference between a NBTI/HCI stressed MOSFET device and a NBTI/HCI unstressed MOSFET device using an inverter chain and a phase comparator and digitalize the phase difference induced by the threshold voltage difference. The proposed sensor circuits achieve a direct correlation between the threshold voltage degradation and the phase difference (a phase difference resolution of 1 ns per 0.01 V threshold voltage shift). Also, the circuits are almost independent of temperature variation due to symmetrical circuit structures. A 45 nm CMOS technology and predictive NBTI/HCI models have been used to implement and evaluate the proposed circuits. The implemented layout size is 18.58 x 7.97 μm2; the post-layout power consumption is 18.57 μW during NBTI/HCI stress mode and 30.86 μW during NBTI/HCI measurement mode on average.

Reverse Nested Miller Compensation Using Current Buffers in a Three-Stage LDO

Abstract: A novel frequency compensation scheme called reverse nested Miller compensation using current buffers (RNMCCB) for three-stage amplifiers is proposed. As opposed to previous reverse nested schemes, our work uses inverting gain stages for both the second and third stages. The outer compensation loop utilizes a current mirror as an inverting current buffer (CB), and the inner loop uses a common-gate amplifier as a CB, creating two left-half-plane (LHP) zeros. We introduce a simple and effective method of placing a resistor in series with a CB for accurate placement of LHP zeros. As a design example of the RNMCCB scheme, we propose a three-stage low dropout voltage regulator (LDO) in a 0.5-?m CMOS process to supply 1.21 V to a load ranging from 1 ?A to 100 mA. Our design goals were to simultaneously achieve very high current efficiency and very low transient output voltage variation. As such, we achieved a 99.95% current efficiency and a maximum load transient output voltage variation of ±48 mV with an output capacitor of 100 nF. Experimental results, in good agreement with theoretical analysis, validate the novel RNMCCB frequency compensation scheme.

Why Dynamic-Element-Matching DACs Work

Abstract: This jump-start tutorial brief explains the principle that underlies all of the published mismatch-scrambling and mismatch-shaping dynamic-element-matching (DEM) digital-to-analog converters (DACs). It explains the apparent paradox of how an all-digital algorithm can cause analog component mismatches to introduce spectrally shaped noise instead of nonlinear distortion, even though the algorithm has no knowledge of the actual mismatches. The concept is first explained in the context of a discrete-time three-level DEM DAC. The results are then generalized to an arbitrary number of levels, to segmented DEM DACs, and to continuous-time DEM DACs.

Design of a 24-GHz CMOS VCO With an Asymmetric-Width Transformer

Abstract: A K-band CMOS voltage-controlled oscillator (VCO) is implemented with a 0.18- ?m radio frequency CMOS process. For low supply voltage operation, a transformer-feedback topology using a transformer is proposed. The analysis of the transformer-feedback VCO is presented. This shows that the inductance ratio of the transformer must be optimized, and asymmetric-width transformers allow the easy optimization and the high Q-factor. Based on this analysis, the transformer design consideration of the transformer feedback VCO is presented. The VCO operates at 24.27 GHz with the phase noise of -100.33 dBc/Hz at 1-MHz offset, and it consumes 7.8 mW from a 0.65-V supply voltage.

Randomness Enhancement Using Digitalized Modified Logistic Map

Abstract: In this brief, a nonlinear digitalized modified logistic map-based pseudorandom number generator (DMLM-PRNG) is proposed for randomness enhancement. Two techniques, i.e., constant parameter selection and output sequence scrambling, are employed to reduce the computation cost without sacrificing the complexity of the output sequence. Statistical test results show that with only one multiplication, DMLM-PRNG passes all cases in SP800-22. Moreover, it passes most of the cases in Crush, one of the test suites of TesuU01. When compared with solutions based on digitized pseudochaotic maps previously proposed in the literature, in terms of randomness quality, our system is as good as a Renyi-map-based PRNG and better than a logistic-map-based PRNG. Moreover, compared with solutions based on a Renyi-map-based PRNG, DMLM-PRNG is better scalable to high digital resolutions with reasonable area overhead.

Phase Frequency Detector With Minimal Blind Zone for Fast Frequency Acquisition

Abstract: Blind zone in a phase-frequency detector (PFD) reduces the input detection range and aggravates cycle slips. This brief analyzes the blind zone in latch-based PFDs and proposes a technique that removes the blind zone caused by the precharge time of the internal nodes. With the proposed technique, the PFD achieves a small blind zone close to the limit imposed by process-voltage-temperature variations. The comparison between the proposed design and previous works is presented. Fabricated in a 130-nm CMOS technology, the measured blind zone is 61 ps, which is smaller than that of the existing topologies by almost 100 ps.

A Generalized Mixed-Radix Algorithm for Memory-Based FFT Processors

Abstract: In this brief, a generalized mixed-radix (GMR) algorithm is proposed for memory-based fast Fourier transform (FFT) processors to support prime-sized and traditional 2n -point FFTs simultaneously It transforms the index to a multidimensional vector for efficient computation By controlling the index vector to satisfy the ?vector reverse? behavior, the GMR algorithm can support not only in-place policy for both computation and I/O data for continuous data flow to minimize the memory size but also multibank memory structures to increase the maximum throughput without memory conflict Finally, a low-complexity implementation of an index vector generator is also proposed for our algorithm

A Design-Oriented Combined Approach for Bifurcation Prediction in Switched-Mode Power Converters

Abstract: In this brief, two different approaches are combined for studying the stability of a buck switching power dc-dc converter and for predicting its bifurcations. Instability indexes derived from both approaches are combined to get a complete design-oriented perspective of bifurcation analysis in terms of practical circuit parameter and to show the effect of each parameter on the system behavior. The first approach is based on the conventional Routh-Hurwitz criterion applied to the averaged converter dynamics, and it is suitable for detecting low-frequency oscillations but is unsuitable for predicting fast-scale period-doubling instabilities. Complementarily, the second approach considers the ripple component before the pulsewidth modulator to quantitatively predict the occurrence of subharmonic oscillations. The usefulness of the combined approach is shown by analytically deriving inequalities that compress the complete design space into simple instability indexes, which, used complementarily, allow a division of the design space into the different instability regions (both period-doubling or fast-scale instability, and Hopf or slow-scale instability). Comparison of the design-oriented complete map obtained combining both methods and their related stability indexes with the results obtained both from time-domain numerical simulations of the exact switched state equations, as well as the stability border obtained from discrete recurrent maps, corroborates the approach.

$M$ -DCSK-Based Chaotic Communications in MIMO Multipath Channels With No Channel State Information

Abstract: We consider chaotic digital communications in multiple-input-multiple-output (MIMO) wireless multipath fading channels. In particular, we focus on systems that employ M -ary differential chaos shift keying (M-DCSK). We consider two transceiver schemes, both of which require no channel state information at either the transmitter or the receiver. The first one employs a distinct chaotic sequence at each transmit antenna to spread the same data symbol and transmits omnidirectionally. At each receive antenna, the corresponding differential detection statistic is formed, and these statistics are then combined with equal gain for symbol detection. The second scheme employs a single chaotic spreading sequence and makes use of adaptive transmit and receive beamforming. The beamformers are updated by using a simple stochastic gradient method that is based on the received signal power and a finite-rate feedback strategy. Simulation results show that both schemes can effectively exploit the spatial diversity of the underlying MIMO system, and the adaptive beamforming scheme significantly outperforms the omnidirectional transmission.

Simultaneous Arithmetic Coding and Encryption Using Chaotic Maps

Abstract: Based on the observation that iterating a skew tent map reversely is equivalent to arithmetic coding, a simultaneous compression and encryption scheme is proposed in which the chaotic map model for arithmetic coding is determined by a secret key and keeps changing. Moreover, the compressed sequence is masked by a pseudorandom keystream generated by another chaotic map. This two-level protection enhances its security level, which results in high key and plaintext sensitivities. The compression performance of our scheme is comparable with arithmetic coding and approaches Shannon's entropy limit.

A New Control Law Based on the Differential Flatness Principle for Multiphase Interleaved DC–DC Converter

Abstract: This brief presents an innovative control law for a distributed dc generation supplied by a dc power source, here, a fuel cell (FC) generator. Basically, an FC is always connected with a power-electronic converter. This kind of system is a nonlinear behavior. Classically, to control the voltage, the current, or the power in the converter, a linearized technique is often used to study the stability and to select the controller parameters of the nonlinear converter. In this brief, a nonlinear-control algorithm based on the flatness property of the system is proposed. Flatness provides a convenient framework for meeting a number of performance specifications on the power converter. Utilizing the flatness property, we propose simple solutions to the system performance and stabilization problems. Design controller parameters are autonomous of the operating point. To validate the proposed method, a prototype FC power converter (1.2-kW four-phase boost converters in parallel) is realized in the laboratory. The proposed control law based on the flatness property is implemented by digital estimation in a dSPACE 1104 controller card. Experimental results with a polymer electrolyte membrane FC of 1200 W and 46 A in the laboratory corroborate the excellent control scheme.

High Power-Supply-Rejection (PSR) Current-Mode Low-Dropout (LDO) Regulator

Abstract: Modern system-on-a-chip (SoC) solutions suffer from limited on-chip capacitance, which means that the switching events of functionally dense ICs induce considerable noise in the supplies. This ripple worsens the accuracy of sensitive analog electronics, such as ADCs, PLLs, and VCOs, etc. Without dropping a substantial voltage, point-of-load (PoL) low-dropout (LDO) regulators reduce (filter) this noise but only as much as their loop gains and bandwidths allow. This brief presents a 5-mA 1.5-μm bipolar current-mode LDO regulator that, with a higher bandwidth current loop, suppresses higher frequency noise by 49 dB (i.e., power-supply rejection) up to 10 MHz with only 68 nF at the output, which is 20 dB better than its voltage-mode counterpart.

Systematic Design Centering of Continuous Time Oversampling Converters

Abstract: We address the practical problem of determining the loop filter component values in a single-loop continuous-time delta sigma modulator. Conventional techniques to design center the converter to achieve a desired noise transfer function are cumbersome and not numerically stable. We present a robust procedure that can be used to determine the loop filter coefficients when real opamps (with finite gain, arbitrary Digital to Analog Converter (DAC) pulse, and multiple internal poles/zeros) are used. The method can also account for excess loop delay. We illustrate our technique with second-order low-pass and fourth-order bandpass examples.

A 1- $\mu\hbox{W}$ 600- $\hbox{ppm}/^{\circ}\hbox{C}$ Current Reference Circuit Consisting of Subthreshold CMOS Circuits

Abstract: A low-power CMOS current reference circuit was developed using a 0.35-μm standard CMOS process technology. The circuit consists of MOSFET circuits operating in the subthreshold region and uses no resistors. It compensates for the temperature effect on mobility μ and threshold voltage VTH of MOSFETs and generates a reference current that is insensitive to temperature and supply voltage. Theoretical analyses and experimental results showed that the circuit generates a stable reference current of 100 nA. The temperature coefficient of the current was 520 ppm/°C at best and 600 ppm/°C on average in the range of 0°C-80°C. The line regulation was 0.2%/V in a supply voltage range of 1.8-3 V. The power dissipation was 1 μW, and the chip area was 0.015 mm2. Our circuit would be suitable for use in subthreshold-operated power-aware large-scale integrations.

Synchronization in Complex Dynamical Networks With Random Sensor Delay

Abstract: This brief proposes a new complex dynamical network model, in which nodes are connected by measured outputs experiencing the random sensor delay. This model is totally different from some existing network models. Then, synchronization in the proposed network model is analyzed by the stochastic stability theory. A sufficient synchronization condition is given to ensure that the proposed network model is exponentially mean-square stable. Theoretical analysis and numerical simulation fully verify the main results.

A Scalable VLSI Architecture for Soft-Input Soft-Output Single Tree-Search Sphere Decoding

Abstract: Multiple-input multiple-output (MIMO) wireless transmission imposes huge challenges on the design of efficient hardware architectures for iterative receivers. A major challenge is soft-input soft-output (SISO) MIMO demapping, often approached by sphere decoding (SD). In this brief, we introduce-to our best knowledge-the first VLSI architecture for SISO SD applying a single tree-search approach. Compared with a soft-output-only base architecture similar to the one proposed by Studer in IEEE J-SAC 2008, the architectural modifications for soft input still allow a one-node-per-cycle execution. For a 4×4 antennas system using quadrature amplitude modulation (QAM) with order 16, the area increases by 57%, and the operating frequency degrades by 34% only.

A 9-bit 80 MS/s Successive Approximation Register Analog-to-Digital Converter With a Capacitor Reduction Technique

Abstract: A 9-bit 80 MS/s successive approximation register analog-to-digital converter (ADC), which is suitable for low power and a small area, is presented. The 9-bit capacitor array consists of only 16 unit capacitors and a coupling capacitor due to the proposed binary-weighted split-capacitor arrays with a merged-capacitor switching technique. The proposed ADC includes a comparator with offset cancellation and uses digital calibration for error correction. The ADC is implemented in a 65-nm complimentary metal-oxide-semiconductor technology and occupies an active area of 0.068 mm2 with a reference buffer. The differential and integral nonlinearities of the ADC are less than 0.37 and 0.40 LSB, respectively. The ADC shows a signal-to-noise-distortion ratio of 50.71 dB, a spurious-free dynamic range of 66.72 dB, and an effective number of bits of 8.13 bits with a 78 MHz sinusoidal input at 80 MS/s. The ADC consumes 3.4 mW with the reference buffer at a 1.0-V supply and achieves a figure of merit of 78 fJ/conversion step.