The design and development of low power electronics has garnered a lot of interest in the recent past due to rise of Internet of Things. The majority of IoT enabled devices rely on reliable data mining and data handling techniques that process both analog and digital data. The present manuscript focusses on the design of an ultra-low power 2- bit flash analog to digital converter. The flash analog to digital converter is implemented using a modified double-tail latch type comparator that consumes a minimal power of 0.65 µW and a delay of 133ps for an operational voltage of 0.6V at 16m technological node. The proposed analog to digital converter is equipped with bubble error correction and digital encoding techniques for fast and reliable data conversion. The proposed analog to digital converter consumes a power of 0.4 mW at the lowest operational voltage of 0.6V for 16nm technological node. The simulation of the proposed flash analog to digital converter yields a sub-milliwatt power consumption at different operational voltage ranging from 0.6V to 1.2V. The low power consumption values suggest the use of proposed flash analog to digital converter in designing next generation of portable, handheld and energy efficient low power electronic devices that are compatible with IoT technologies.

Design of Low Power 2-Bit Flash ADC using High Performance Dynamic Double Tail Comparator

In recent years, implantable biomedical devices like cardiac pacemaker, defibrillators, cochlear implants, visual prosthesis etc. have gained immense importance in the personal health monitoring system. Most of these devices are battery powered. The life span of a pacemaker is expected to be between 10 and 12 years. This shows the importance of having an ultra-low power design technique to improve the reliability and battery life of the system. To achieve this, power draws from the battery must be kept low. Analog-to-Digital Convertor (ADC) is a main block in the front-end sensing unit of an implant for measurements of various biophysiological signals. This is the most power consuming unit in the system. ADC alone consumes about 30%–35% of the total power. This work surveys various successive approximation ADC designs for biomedical signal acquisition, in terms of power consumption, signal to noise distortion ratio, sampling rate, resolution and Figure of Merit. The different switching schemes for capacitive DAC are also surveyed. 

Design Approaches of Ultra-Low Power SAR ADC for Biomedical Systems - A Review

A high-speed low-noise comparator with an auxiliary inverter-based (AIB) preamplifier is proposed in this brief. The preamplifier adopts an inverter-based input pair without tail transistors, which is well-suitable for low-supply-voltage applications, especially in deep submicrometer technologies. Moreover, it achieves high bandwidth and low noise with high current efficiency. Dynamic common-mode feedback combined with a secondary inverter-based input pair regulates the output common-mode (CM) voltage of the preamplifier by itself against PVT and input CM voltage sensitivity without complex control logic and quiescent current. Embedded in a 200 MS/s 16-bit successive-approximation-register (SAR) analog-to-digital converter (ADC) in standard 28-nm CMOS technology, the proposed comparator achieves a 68.1-ps delay at a 50- <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\mu \text{V}$ </tex-math></inline-formula> differential input voltage and a root-mean-square input-referred noise of 45.6 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\mu \text{V}_{\mathrm {rms}}$ </tex-math></inline-formula> under the 1-V power supply. 

A High-Speed Low-Noise Comparator With Auxiliary-Inverter-Based Common Mode-Self-Regulation for Low-Supply-Voltage SAR ADCs

A high-speed low-noise comparator with an auxiliary inverter-based (AIB) preamplifier is proposed in this brief. The preamplifier adopts an inverter-based input pair without tail transistors, which is well-suitable for low-supply-voltage applications, especially in deep submicrometer technologies. Moreover, it achieves high bandwidth and low noise with high current efficiency. Dynamic common-mode feedback combined with a secondary inverter-based input pair regulates the output common-mode (CM) voltage of the preamplifier by itself against PVT and input CM voltage sensitivity without complex control logic and quiescent current. Embedded in a 200 MS/s 16-bit successive-approximation-register (SAR) analog-to-digital converter (ADC) in standard 28-nm CMOS technology, the proposed comparator achieves a 68.1-ps delay at a 50-<inline-formula> <tex-math notation="LaTeX">$\mu \text{V}$ </tex-math></inline-formula> differential input voltage and a root-mean-square input-referred noise of 45.6 <inline-formula> <tex-math notation="LaTeX">$\mu \text{V}_{\mathrm {rms}}$ </tex-math></inline-formula> under the 1-V power supply.

We have designed a fully-integrated analog CMOS cognitive image sensor based on a two-layer artificial neural network and targeted to low-resolution image classification. We have used a single poly 180 nm CMOS process technology, which includes process modules for realizing the building blocks of the CMOS image sensor. Our design includes all the analog sub-circuits required to perform the cognitive sensing task, from image sensing to output classification decision. The weights of the network are stored in single-poly floating-gate memory cells, using a single transistor per analog weight. This enables the classifier to be intrinsically reconfigurable, and to be trained for various classification problems, based on low-resolution images. As a case study, the classifier capability is tested using a low-resolution version of the MNIST dataset of handwritten digits. The circuit exhibits a classification accuracy of 87.8%, that is comparable to an equivalent software implementation operating in the digital domain with floating point data precision, with an average energy consumption of 6 nJ per inference, a latency of 22.5 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\mu \text{s}$ </tex-math></inline-formula> and a throughput of up to 133.3 thousand inferences per second. 

https://zenodo.org/record/7494541/files/IEEE%20Access%20-%20%202022%20-%20%20Zambrano%20-%20All-Analog_Silicon_Integration_of_Image_Sensor_and_Neural_Computing_Engine_for_Image_Classification.pdf

All-Analog Silicon Integration of Image Sensor and Neural Computing Engine for Image Classification

This letter presents a low-power dynamic comparator for ultralow power applications. The prototype is designed in a 65-nm CMOS process with a supply voltage of 1 V and is compared against the widely used double tail latch comparator in terms of power consumption and input referred rms noise. The addition of cross-coupled devices to the input differential pair prevents the comparator internal nodes from fully discharging to ground in contrast to the conventional architecture. This reduces the power consumption while achieving similar noise levels. Measurements demonstrate that the proposed comparator achieves an input referred rms noise voltage of 220 $\mu \text{V}$ against 210 $\mu \text{V}$ for the conventional comparator with a 30% reduction in power. The proposed circuit consumes 0.19-pJ energy per comparison.

A Low-Power 1-V Supply Dynamic Comparator

Precision multiply-by-2 amplifiers have been researched intensively due to their use in pipelined analog-to-digital converters. For integer gains greater than 2, not much work has been reported. This work presents a multiply-by-n switched capacitor amplifier, for n greater than 2, whose gain is insensitive to capacitor mismatch. Simulation results show that the variation in gain due to capacitance mismatch is much lesser than conventional architectures.

Subhash Chevella

Papers

A Low-Power 1-V Supply Dynamic Comparator

Multiply-by-n Switched Capacitor Amplifier Insensitive to Capacitance Mismatch