http://www-lia.deis.unibo.it/Courses/SistInt/articoli/max-min-ant.pdf

MAX-MIN Ant system

A unified view of metaheuristics This book provides a complete background on metaheuristics and shows readers how to design and implement efficient algorithms to solve complex optimization problems across a diverse range of applications, from networking and bioinformatics to engineering design, routing, and scheduling. It presents the main design questions for all families of metaheuristics and clearly illustrates how to implement the algorithms under a software framework to reuse both the design and code. Throughout the book, the key search components of metaheuristics are considered as a toolbox for: Designing efficient metaheuristics (e.g. local search, tabu search, simulated annealing, evolutionary algorithms, particle swarm optimization, scatter search, ant colonies, bee colonies, artificial immune systems) for optimization problems Designing efficient metaheuristics for multi-objective optimization problems Designing hybrid, parallel, and distributed metaheuristics Implementing metaheuristics on sequential and parallel machines Using many case studies and treating design and implementation independently, this book gives readers the skills necessary to solve large-scale optimization problems quickly and efficiently. It is a valuable reference for practicing engineers and researchers from diverse areas dealing with optimization or machine learning; and graduate students in computer science, operations research, control, engineering, business and management, and applied mathematics.

/pdf/metaheuristics-from-design-to-implementation-1vqdfv8nk9.pdf

Metaheuristics: From Design to Implementation

Variable neighborhood search: Principles and applications

This chapter contains sections titled: Combinatorial Optimization, The ACO Metaheuristic, How Do I Apply ACO?, Other Metaheuristics, Bibliographical Remarks, Things to Remember, Thought and Computer Exercises

https://wwwmayr.informatik.tu-muenchen.de/lehre/1999SS/optprak/BC.04-DorDic-NIO99.pdf

The ant colony optimization meta-heuristic

The field of ACO algorithms is very lively, as testified, for example, by the successful biannual workshop (ANTS—From Ant Colonies to Artificial Ants: A Series of International Workshops on Ant Algorithms; http://iridia.ulb.ac.be/~ants/) where researchers meet to discuss the properties of ACO and other ant algorithms, both theoretically and experimentally.

The Ant Colony Optimization Metaheuristic: Algorithms, Applications, and Advances

A new adaptive multi-start technique for combinatorial global optimizations

In this paper we presen t a rank-one update method for updating reduced-order models of interconnect parasitics when driv e resistances or load capacitances change, as commonly occurs during timing analysis. These rank-one updates are extremely inexpensive, do not require reexamining the original in terconnect netw ork, and most importantly are provably equivalent to rereducing the original netw ork. This abstract contains the proof only for the case of varying the driver resistance, but examples are given to sho w that the exactness holds more generally. In particular, a cross-talk case is examined where the conductance matrix is singular.

https://vlsicad.ucsd.edu/Publications/Conferences/108/c108.pdf

On switch factor based analysis of coupled RC interconnects

The performance of high-speed VLSI circuits is increasingly limited by interconnect coupling noise. In this paper we present a closed-form crosstalk noise model with accuracy comparable to that of SPICE for an arbitrary ramp input. We also develop a simplified delay model for estimating delays on coupled RC lines considering input slew times for both agressor and victim lines. We then apply our model along with SPICE simulation to perform various studies of delay uncertainty in coupled interconnects. With respect to the effects of changing aggressor slew time on victim delay (i.e., delay variation), we observe that the victim delay is worst when the aggressor is switching very fast (e.g., step input). For local interconnects the delay variation (change in victim delay with varying input slew) can be as high as 70%. On the other hand, delay variation is around 10% for global interconnects. We also observe that the difference between minimum and maximum delay (i.e., delay uncertainty) decreases significantly as slew times are increased. Delay uncertainty on the victim wire is high for global wires as compared to local wires, a consequence of differing ratios of coupling to parallel-plate capacitance, and wire to load capacitance. We believe that our noise and delay analytical models form an effective basis for methodologies that lead to less over-design and guard-banding in high-performance system designs.

/pdf/noise-and-delay-uncertainty-studies-for-coupled-rc-4wftfubq83.pdf

Noise and delay uncertainty studies for coupled RC interconnects

Interconnect tuning is an increasingly critical degree of freedom in the physical design of high-performance VLSI systems. By interconnect tuning, we refer to the selection of line thicknesses, widths and spacings in multi-layer interconnect to simultaneously optimize signal distribution, signal performance, signal integrity, and interconnect manufacturability and reliability. This is a key activity in most leading-edge design projects, but has received little attention in the literature. Our work provides the first technology-specific studies of interconnect tuning in the literature. We center on global wiring layers and interconnect tuning issues related to bus routing, repeater insertion, and choice of shielding/spacing rules for signal integrity and performance. We ad-dress four basic questions. (1) How should width and spacing be allocated to maximize performance for a given line pitch? (2) For a given line pitch, what criteria affect the optimal interval at which repeaters should be inserted into global interconnects? (3) Under what circumstances are shield wires the optimum technique for improving interconnect performance? (4) In global interconnect with repeaters, what other interconnect tuning is possible? Our study of question (4) demonstrates a new approach of offsetting repeater placements that can reduce worst-case cross-chip delays by over 30% in current technologies.

/pdf/interconnect-tuning-strategies-for-high-performance-ics-1v0pluasy6.pdf

Interconnect tuning strategies for high-performance ICs

We address the two-pole simulation of interconnect trees via the moment matching technique. We simulate the interconnect network by modeling the distributed lines with non-uniform m lumped segments and using the two-pole methodology. To this end, we derive new non-uniform equivalent circuits which match the general distributed line transfer function up to the second term. Using the recursive equation for the admittance of a tree, we give the exact expressions for the first and second moments of the transfer function of the interconnect tree. Our results show that delay estimates using our method are within 13% of SPICE-computed delays. As routing trees become bigger and interconnection lines become longer, e.g., in MCM design, our approach has advantages in both accuracy and simulation complexity.

/pdf/two-pole-analysis-of-interconnection-trees-1lhc00u6iz.pdf

Sudhakar Muddu

Papers

A new adaptive multi-start technique for combinatorial global optimizations

On switch factor based analysis of coupled RC interconnects

Noise and delay uncertainty studies for coupled RC interconnects

Interconnect tuning strategies for high-performance ICs

Two-pole analysis of interconnection trees