Automatic music transcription uses computational algorithms to covert a music audio into some form of music notation. Automatic music transcription is very important for applications like music mixing, song recommendation and music information retrieval. It is a challenging task involving the domains of signal processing and artificial intelligence. Though there are many works on automatic music transcription for western music, there are very few works for automatic music transcription for Indian classical music, especially Carnatic music. Automatic music transcription for Carnatic music is very challenging due to variations in the swars/note frequencies. Due to the variations, it becomes difficult to detect the Raga and transcribe the music. In this work, a deep learning LSTM based automatic music transcription system is proposed for Carnatic music. The note detection is solved as the image classification problem using a modified Visual Geometry Group Network (VGGNet). The sequence of notes is classified into 72 Melakartha ragas using an LSTM classifier and provides better accuracy when compared to existing methods.

Deep Learning Long Short-Term Memory based Automatic Music Transcription System for Carnatic Music

The embodiment of the invention discloses a low dropout regulator. An output end of a first power tube in the low dropout regulator is connected with an input end of a second power tube; a control end of the second power tube is connected with the output end of a mid-value voltage stabilizer; the input end of the mid-value voltage stabilizer is connected with an input power supply; the scope of an input voltage value of the input power supply is more than 0 but less than or equal to 2 times of the maximum working voltage of the first power tube or the second power tube; and a voltage value at the output end of the mid-value voltage stabilizer is a difference value of the input voltage value of the input power supply and the maximum working voltage of the first power tube or the second power tube. According to the technical scheme provided by the embodiment of the invention, the second power tube and the mid-value voltage stabilizer are additionally arranged, so that the scope of the working voltage of the low dropout regulator is effectively widened under the condition of only using the power tube with low threshold voltage, the low dropout regulator and the other circuits are more easily integrated onto a same chip, and thus the cost is greatly lowered.

Low dropout regulator

Meeting the requirements of low-power design is a real challenge in the semiconductor industry. In the past few years, many new methodologies have been introduced to help engineers dealing with the growing complexity of chip design. One of such methodologies is the power-intent description based on the Unified Power Format (UPF), which defines, for the first time, a structured standard language to annotate power-intent to a design. This work aims to further improve the deployment of UPF standard in the industry, proposing a methodology that enables design editing and restructuring with automatic detection of power-intent inconsistencies. This work demonstrates how to highly correlate the UPF and Hardware Description Languages (HDL) in order to track power-intent inconsistencies due to modifications in either of the descriptions. The final goal will be to offer in the long term a fully automated solution which captures the changes in HDL code and modifies the UPF accordingly (and vice-versa). A test-case is presented to illustrate the capabilities of the developed design methodology.

A Methodology for Automated Consistency Checking Between Different Power-Aware Descriptions

Mixed-signal components, such as low dropouts (LDOs) and phase locked loops (PLLs), are widely used inside the on-chip power management fabric of low power integrated system-on-chip (SoC) designs. The digital brain of the power management logic that is responsible for regulating the power delivery to different power domains in the chip has to consider the real time latencies of the analog components, which otherwise leads to functional errors in the domains being driven. The latencies may be viewed as contracts between the digital and the analog. This article presents an approach for generating assertions for protecting such mixed-signal latency contracts and using them to rule out timing bugs in the power management logic. Our tool flow enables the verification of the power management fabric, combining a novel mixed-signal assertion checking method in a simulation setting, and a full formal verification method for the digital brain of the power management logic. To the best of our knowledge, this is the first framework where assertions are used for binding analog latency contracts on the digital logic of power management.

Assertions for Protecting Mixed-Signal Latency Contracts in Power Management

Meeting the requirements of low-power design is a real challenge in the semiconductor industry. In the past few years, many new methodologies have been introduced to help engineers dealing with the growing complexity of chip design. One of such methodologies is the power-intent description based on the Unified Power Format (UPF), which defines, for the first time, a structured standard language to annotate power-intent to a design. This work aims to further improve the deployment of UPF standard in the industry, proposing a methodology that enables design editing and manipulation with automatic detection of power-intent inconsistencies. This work demonstrates how to highly correlate the UPF and Hardware Description Language (HDL) in order to track power-intent inconsistencies due to modifications in either of the descriptions. The final goal will be to offer in the long term a completely automated tool which captures the changes in HDL code and modifies the UPF accordingly (and vice-versa). A test-case is presented to illustrate the capabilities of the developed design methodology.

Towards consistency checking between HDL and UPF descriptions

System on Chip (SoC) designs today have a large number of power domains regulated by complex on-chip power management logic. The power management logic is primarily digital in nature, but it relies on analog components such as Low Dropout Regulators (LDO) and Phase-Locked Loops (PLL) for delivery of regulated voltages and clock frequencies. In low power designs, such analog components may also be powered down at times, and hence power domains are defined around modules containing these components. The digital brain of the power management logic must correctly consider the latencies of the analog components in the power management fabric while switching the power domains driven by these components. This is a task which has become extremely complex by virtue of the multitude of LDOs and PLLs in a modern integrated circuit, and the numerous domains that they drive. This paper presents, for the first time, a formal verification methodology for automatically generating the necessary assertions from an extended syntax of the Unified Power Format (UPF) and proving them on the power management logic using available industrial formal verification tools.

Formal Verification of Power Management Logic with Mixed-Signal Domains

The ability to produce music is perhaps the most endearing quality in human beings. The sounds of music all over the world stand united on the 12 notes in an octave. While the physics of music and the incredible ability of human beings to perceive and reproduce notes and rhythm has been the subject of significant research spanning centuries, Indian classical music, by virtue of its system of Ragas, offers unique characteristics and opportunities to study the relation between the syntactic fabric of music and its mystical qualities. In order to be able to model and discover structures that explain the various classifications of the Ragas, an essential first step is to develop a formal model for the Ragas. The basic rules of Ragas such as Thaat, Arohana–Avarohana, etc., and Raga classification rules such as Raganga Padhati help us in building a formal model for the Ragas. Building such models help us to classify Ragas and to rate music scores based on Ragas. The goal of this research is to dive into the realms of Indian classical music with the ambition of learning the well perceived yet unexplained connections between the syntactic structure of Ragas and their effects in a multifaceted way.

On the Deep Structure of Ragas and Analytic Rating of Music Scores

In order to cope up with the growing performance demands, rapid increase in the transistor density in modern on-chip cores has made power dissipation a primary concern for the chip-designers. Chip temperature surpasses thermal limits at multiple hot-spots which significantly affects its performance and reliability. This work explores the possibility of readjusting the task schedules intelligently under real-time constraints, so that the on-chip power and thermal profiles remain within admissible limits. Our target platform is a homogeneous multicore environment with Dynamic Voltage and Frequency Scaling (DVFS) capabilities. We use multi-objective optimization techniques to restrict power dissipation under thermal constraints. We also use Reinforcement Learning (RL) using Proximal Policy Optimization (PPO) to readjust task schedules based on a set of proposed reward functions and energy optimization processes. We show the efficacy of our methodology by running the algorithm on a model test case and comparing the results with other state-of-the-art methods.

An RL based Approach for Thermal-Aware Energy Optimized Task Scheduling in Multi-core Processors

Background: Threatened abortion is a relatively common complication during pregnancy. Inadequate production of endogenous progesterone is implicated as a risk factor for miscarriages. Thus, supplementation of external progesterone can be used as a preventive strategy in these women. Dydrogesterone a stereoisomer of progesterone has a good safety and tolerability profile and is known to effectively prevent pregnancy loss in women with threatened miscarriage, however, real-world data safety and effectiveness analysis of dydrogesterone in Indian patients was lacking. Therefore, this real-world retrospective analysis of the case reports was done to evaluate the safety, effectiveness, compliance, and tolerability of oral dydrogesterone in the treatment of women with threatened abortion.Methods: Data was collected from 194 obstetricians and gynaecologists in India, on the use of oral dydrogesterone in women presenting with threatened abortion in the first trimester of pregnancy.Results: Completed case report forms of patients who met the eligibility criteria (n = 617) were considered for the analysis. The main presenting symptom was vaginal bleeding/spotting with an additional symptom of abdominal cramp/pelvic pain/low back pain in 364 (69.07%) patients. Miscarriage was reported in 45 (7.29%) patients and 23 (3.98%) patients needed surgical intervention before 20 weeks of gestation with dydrogesterone treatment. The median time for relief of symptoms from the start of dydrogesterone tablets was 3.32 days for low back pain, 3.9 days for abdominal pain, and 4.37 days for the establishment of hemostasis. Treatment with dydrogesterone was found to be well-tolerated and adverse events were reported in 3.72% of the patients.Conclusions: This retrospective analysis suggests that dydrogesterone is safe and effective in reducing the incidence of pregnancy loss in women with threatened abortion.

Sudipa Mandal

Papers

Formal Verification of Power Management Logic with Mixed-Signal Domains

On the Deep Structure of Ragas and Analytic Rating of Music Scores

An RL based Approach for Thermal-Aware Energy Optimized Task Scheduling in Multi-core Processors

Assertions for Protecting Mixed-Signal Latency Contracts in Power Management

Real-world evaluation of safety and effectiveness of dydrogesterone in the management of threatened abortion