S
Sung Hyun Jo
Researcher at University of Michigan
Publications - 82
Citations - 8649
Sung Hyun Jo is an academic researcher from University of Michigan. The author has contributed to research in topics: Resistive random-access memory & Electrode. The author has an hindex of 32, co-authored 80 publications receiving 7767 citations.
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Nanoscale Memristor Device as Synapse in Neuromorphic Systems
TL;DR: A nanoscale silicon-based memristor device is experimentally demonstrated and it is shown that a hybrid system composed of complementary metal-oxide semiconductor neurons and Memristor synapses can support important synaptic functions such as spike timing dependent plasticity.
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Short-term memory to long-term memory transition in a nanoscale memristor.
Ting Chang,Sung Hyun Jo,Wei Lu +2 more
TL;DR: This study shows experimentally that the retention loss in a nanoscale memristor device bears striking resemblance to memory loss in biological systems and confirms that not only the shape or the total number of stimuli is influential, but also the time interval between stimulation pulses plays a crucial role in determining the effectiveness of the transition.
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High-density crossbar arrays based on a Si memristive system.
Sung Hyun Jo,Kuk-Hwan Kim,Wei Lu +2 more
TL;DR: Large-scale (1 kb) high-density crossbar arrays using a Si-based memristive system with excellent reproducibility and reliability are demonstrated and facilitates further studies on hybrid nano/CMOS systems.
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CMOS compatible nanoscale nonvolatile resistance switching memory.
Sung Hyun Jo,Wei Lu +1 more
TL;DR: The results suggest that the CMOS compatible, nanoscale Si-based resistance switching devices may be well suited for ultrahigh-density memory applications.
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Programmable resistance switching in nanoscale two-terminal devices.
Sung Hyun Jo,Kuk-Hwan Kim,Wei Lu +2 more
TL;DR: It is shown that in nanoscale two-terminal resistive switches the resistance switching can be dominated by the formation of a single conductive filament, making them well suited for memory or logic operations using conventional or emerging hybrid nano/CMOS architectures.