A low temporal noise and high dynamic range CMOS image sensor is developed. A 1Mpixel CMOS image sensor with column-parallel folding-integration and cyclic ADCs has 80μVrms (1.2e-) temporal noise, 82 dB dynamic range using 64 samplings in the folding-integration ADC mode. Very high variable gray-scale resolution of 13b through 19b is attained by changing the number of samplings of pixel outputs. The implemented CMOS image sensor using a 0.18-μm technology has the sensitivity of 10-V/lx·s, the conversion gain of 67- μV/e-, and linear digital code range of more than 4 decades.

A Low-Noise High Intrascene Dynamic Range CMOS Image Sensor With a 13 to 19b Variable-Resolution Column-Parallel Folding-Integration/Cyclic ADC

The Quanta Image Sensor (QIS) was conceived when contemplating shrinking pixel sizes and storage capacities, and the steady increase in digital processing power. In the single-bit QIS, the output of each field is a binary bit plane, where each bit represents the presence or absence of at least one photoelectron in a photodetector. A series of bit planes is generated through high-speed readout, and a kernel or “cubicle” of bits (x, y, t) is used to create a single output image pixel. The size of the cubicle can be adjusted post-acquisition to optimize image quality. The specialized sub-diffraction-limit photodetectors in the QIS are referred to as “jots” and a QIS may have a gigajot or more, read out at 1000 fps, for a data rate exceeding 1 Tb/s. Basically, we are trying to count photons as they arrive at the sensor. This paper reviews the QIS concept and its imaging characteristics. Recent progress towards realizing the QIS for commercial and scientific purposes is discussed. This includes implementation of a pump-gate jot device in a 65 nm CIS BSI process yielding read noise as low as 0.22 e− r.m.s. and conversion gain as high as 420 µV/e−, power efficient readout electronics, currently as low as 0.4 pJ/b in the same process, creating high dynamic range images from jot data, and understanding the imaging characteristics of single-bit and multi-bit QIS devices. The QIS represents a possible major paradigm shift in image capture.

The Quanta Image Sensor: Every Photon Counts.

A low temporal read noise and high conversion gain reset-gate-less CMOS image sensor (CIS) has been developed and demonstrated for the first time at photoelectron-counting-level imaging. To achieve a high pixel conversion gain without fine or special processes, the proposed pixel has two unique structures: 1) coupling capacitance between the transfer gate and floating diffusion (FD) and 2) coupling capacitance between the reset gate and FD, for removing parasitic capacitances around the FD node. As a result, a CIS with the proposed pixels is able to achieve a high pixel conversion gain of $220~\mu \text{V}/\text{e}^{ {{-}}}$ and a low read noise of 0.27e $^{-}_{\text {rms}}$ using correlated multiple-sampling-based readout circuitry.

A 0.27e $^{-}_{\text {rms}}$ Read Noise 220- $\mu \text{V}/\text{e}^{-}$ Conversion Gain Reset-Gate-Less CMOS Image Sensor With 0.11- $\mu \text{m}$ CIS Process

A vision chip is a high-speed and compact vision system that integrates an image sensor and parallel image processors on a single silicon die. Nowadays, high-speed vision chips with powerful recognition capabilities are greatly demanded in applications such as: industrial automation, security, entertainment, robotic vision, and human-machine interaction. Some 100-to-1,000fps vision chips have been reported [1-4]. These chips integrate pixel-parallel and row-parallel SIMD array processors to speed up low- and mid-level image processing [1,2]. Recently, microprocessors (MPU) have been embedded to carry out high-level image processing [3,4]. Although excellent in low- and mid-level processing, these systems are poor in high-level feature vector (FV) recognition tasks due to the von Neumann bottleneck of the MPU. As a consequence, these chips can no longer achieve 1,000fps system-level performance, from image acquisition to high-level feature-recognition processing.

7.3 A 1000fps vision chip based on a dynamically reconfigurable hybrid architecture comprising a PE array and self-organizing map neural network

For low-light-level imaging, the performance of a CMOS image sensor (CIS) is usually limited by the temporal readout noise (TRN) generated from its analog readout circuit chain. Although a sub-electron TRN level can be achieved with a high-gain pixel-level amplifier, the pixel uniformity is highly impaired up to a few percent by its open-loop amplifier structure [1]. The TRN can be suppressed without this penalty by employing either a high-gain column-level amplifier [2] or a correlated multiple sampling (CMS) technique [3–5]. However, only 1-to-2 electron TRN level has been reported with the individual use of these approaches [2–5], and the low-frequency noise of the in-pixel source follower i.e. 1/fand RTS noise is a further limitation. Therefore, by implementing a high-gain column-level amplifier and CMS technique together with an in-pixel buried-channel source follower (BSF) [6], the TRN level can be reduced even further.

A 0.7e − rms -temporal-readout-noise CMOS image sensor for low-light-level imaging

For low-noise complementary metal-oxide-semiconductor (CMOS) image sensors, the reduction of pixel source follower noises is becoming very important Column-parallel high-gain readout circuits are useful for low-noise CMOS image sensors This paper presents column-parallel high-gain signal readout circuits, correlated multiple sampling (CMS) circuits and their noise reduction effects In the CMS, the gain of the noise cancelling is controlled by the number of samplings It has a similar effect to that of an amplified CDS for the thermal noise but is a little more effective for 1/f and RTS noises Two types of the CMS with simple integration and folding integration are proposed In the folding integration, the output signal swing is suppressed by a negative feedback using a comparator and one-bit D-to-A converter The CMS circuit using the folding integration technique allows to realize a very low-noise level while maintaining a wide dynamic range The noise reduction effects of their circuits have been investigated with a noise analysis and an implementation of a 1Mpixel pinned photodiode CMOS image sensor Using 16 samplings, dynamic range of 594 dB and noise level of 19 e(-) for the simple integration CMS and 75 dB and 22 e(-) for the folding integration CMS, respectively, are obtained

https://www.mdpi.com/1424-8220/10/10/9139/pdf

Column-parallel correlated multiple sampling circuits for CMOS image sensors and their noise reduction effects.

Low-noise CMOS image sensors (CIS) employing column-parallel amplifiers that significantly reduce temporal noise, as well as electron-multiplication CCD (EM-CCD) image sensors are becoming popular for very-low-light-level imaging. These low-noise imagers with high-gain amplification in either the charge or voltage domains sacrifice the intra-scene dynamic range. Scientific applications of solid-state imagers strongly require very low temporal noise and wide intra-scene dynamic range as well as very high gray-scale resolution. A column-parallel analog-to-digital converter (ADC) and column-level signal processing in CISs are key techniques to meet these requirements. Single-slope [1,2], successive-approximation [3] and cyclic ADCs [4] are widely used for the column-parallel ADC in CMOS imagers. However, these ADCs require additional gain enhancements to achieve very low temporal noise. A recently reported [5] delta-sigma (ΔΣ) ADC has an attractive feature that low temporal noise and high resolution can be simultaneously attained by an oversampling technique. However, for very high resolution, a high number of samplings per pixel output, e.g., more than 360 samplings for 16b, is required.

An 80μV rms -temporal-noise 82dB-dynamic-range CMOS Image Sensor with a 13-to-19b variable-resolution column-parallel folding-integration/cyclic ADC

Resolution Column-Parallel Folding- Integration/Cyclic ADC

A 1Mpixel CMOS image sensor with column-parallel folding-integration and cyclic ADCs has 80μVrms (1.2e ) temporal noise, 82dB dynamic range using 64 samplings in the folding-integration ADC mode. Very high variable gray-scale resolution of 13b through 19b is attained by changing the number of samplings of pixel outputs.

/pdf/14-1-a-low-noise-wide-dynamic-range-cmos-image-sensor-using-pqkkexutsf.pdf

Sungho Suh

Papers

A Low-Noise High Intrascene Dynamic Range CMOS Image Sensor With a 13 to 19b Variable-Resolution Column-Parallel Folding-Integration/Cyclic ADC

Column-parallel correlated multiple sampling circuits for CMOS image sensors and their noise reduction effects.

An 80μV rms -temporal-noise 82dB-dynamic-range CMOS Image Sensor with a 13-to-19b variable-resolution column-parallel folding-integration/cyclic ADC

Resolution Column-Parallel Folding- Integration/Cyclic ADC

14-1 A Low Noise Wide Dynamic Range CMOS Image Sensor Using a Column-Parallel Folding-Integration/Cyclic ADC