Swathi Gurumani

TL;DR: A case study using HLS for a full H.264 decoder for an application with over 6000 lines of code and over 100 functions, and the experience on code conversion for synthesizability, various HLS optimizations, HLS limitations while dealing with complex input code, and general design insights are shared.

TL;DR: A generic IoT device design flow is presented and platform choices for IoT devices to efficiently tradeoff cost, power, performance and volume constraints are discussed: CPU-based systems and custom platforms that contain hardware accelerators including embedded GPUs and FPGAs.

TL;DR: A new HLS flow is introduced that integrates with Altera's Quartus synthesis and fast placement and routing tool to obtain realistic post-PAR delay estimates and enables an iterative flow that improves the performance of the design with both behavioral-level and circuit-level optimizations using realistic delay information.

TL;DR: A customizable NoC architecture along with a directory-based data-sharing mechanism for an existing CUDA-to-FPGA (FCUDA) flow is presented to enable scalability of the system and improve overall system performance.

TL;DR: This paper couple HLS and logic synthesis synergistically so multi-cycle paths can be identified and optimised coherently across both behavioral and logic levels, and proves that the technique examines all reachable circuit state and finds multi- cycle paths including control flow and guarding conditions that improve the flexibility and power of the technique.