Physical mechanisms responsible for nondestructive single-event effects in digital microelectronics are reviewed, concentrating on silicon MOS devices and integrated circuits. A brief historical overview of single-event effects in space and terrestrial systems is given, and upset mechanisms in dynamic random access memories, static random access memories, and combinational logic are detailed. Techniques for mitigating single-event upset are described, as well as methods for predicting device and circuit single-event response using computer simulations. The impact of technology trends on single-event susceptibility and future areas of concern are explored.

Basic mechanisms and modeling of single-event upset in digital microelectronics

Silicon-on-insulator (SOI) technologies have been developed for radiation-hardened applications for many years and are rapidly becoming a main-stream commercial technology. The authors review the total dose, single-event effects, and dose rate hardness of SOI devices. The total dose response of SOI devices is more complex than for bulk-silicon devices due to the buried oxide. Radiation-induced trapped charge in the buried oxide can increase the leakage current of partially depleted transistors and decrease the threshold voltage and increase the leakage current of fully depleted transistors. Process techniques that reduce the net amount of radiation-induced positive charge trapped in the buried oxide and device design techniques that mitigate the effects of trapped charge in the buried oxide have been developed to harden SOI devices to bulk-silicon device levels. The sensitive volume for charge collection in SOI technologies is much smaller than for bulk-silicon devices potentially making SOI devices much harder to single-event upset (SEU). However, bipolar amplification caused by floating body effects can significantly reduce the SEU hardness of SOI devices. Body ties are used to reduce floating body effects and improve SEU hardness. SOI ICs are completely immune to classic four-layer p-n-p-n single-event latchup; however, floating body effects make SOI ICs susceptible to single-event snapback (single transistor latch). The sensitive volume for dose rate effects is typically two orders of magnitude lower for SOI devices than for bulk-silicon devices. By using body ties to reduce bipolar amplification, much higher dose rate upset levels can be achieved for SOI devices than for bulk-silicon devices.

Radiation effects in SOI technologies

Interferometric lithography (IL), the interference of a small number of coherent optical beams, is a powerful technique for the fabrication of a wide array of samples of interest for nanoscience and nanotechnology. The techniques and limits of IL are discussed with particular attention to the smallest scales achievable. With immersion techniques, the smallest pattern size for a single exposure is a half-pitch of /spl lambda//4n where /spl lambda/ is the optical wavelength and n is the refractive index of the immersion material. Currently with a 193-nm excimer laser source and H/sub 2/O immersion, this limiting dimension is /spl sim/34 nm. With nonlinear spatial frequency multiplication techniques, this limit is extended by factors of 1/2, 1/3, etc.-extending well into the nanoscale regime. IL provides an inexpensive, large-area capability as a result of its parallelism. Multiple exposures, multiple beams, and mix-and-match with other lithographies extend the range of applicability. Imaging IL provides an approach to arbitrary structures with comparable resolution. Numerous application areas, including nanoscale epitaxial growth for semiconductor heterostructures; nanofluidics for biological separations; nanomagnetics for increased storage density; nanophotonics including distributed feedback and distributed Bragg reflectors, two- and three-dimensional photonic crystals, metamaterials, and negative refractive index materials for enhanced optical interactions are briefly reviewed.

Optical and Interferometric Lithography - Nanotechnology Enablers

The production and propagation of single-event transients in scaled metal oxide semiconductor (CMOS) digital logic circuits are examined. Scaling trends to the 100-nm technology node are explored using three-dimensional mixed-level simulations, including both bulk CMOS and silicon-on-insulator (SOI) technologies. Significant transients in deep submicron circuits are predicted for particle strikes with linear energy transfer as low as 2 MeV-cm/sup 2//mg, and unattenuated propagation of such transients can occur in bulk CMOS circuits at the 100-nm technology node. Transients approaching 1 ns in duration are predicted in bulk CMOS circuits. Body-tied SOI circuits produce much shorter transients than their bulk counterparts, making them more amenable to transient filtering schemes based on temporal redundancy. Body-tied SOI circuits also maintain a significant advantage in single-event transient immunity with scaling.

Production and propagation of single-event transients in high-speed digital logic ICs

As the size of the SRAM cache and DRAM memory grows in servers and workstations, cosmic-ray errors are becoming a major concern for systems designers and end users. Several techniques exist to detect and mitigate the occurrence of cosmic-ray upset, such as error detection, error correction, cache scrubbing, and array interleaving. This paper covers the tradeoffs of these techniques in terms of area, power, and performance penalties versus increased reliability. In most system applications, a combination of several techniques is required to meet the necessary reliability and data-integrity targets.

Cache and memory error detection, correction, and reduction techniques for terrestrial servers and workstations

Large-scale three-dimensional (3D) device simulations, focused ion microscopy, and broadbeam heavy-ion experiments are used to determine and compare the SEU-sensitive volumes of bulk-Si and SOI CMOS SRAMs. Single-event upset maps and cross-section curves calculated directly from 3D simulations show excellent agreement with broadbeam cross section curves and microbeam, charge collection and upset images for 16 K bulk-Si SRAMs. Charge-collection and single-event upset (SEU) experiments on 64 K and 1 M SOI SRAMs indicate that drain strikes can cause single-event upsets in SOI ICs. 3D simulations do not predict this result, which appears to be due to anomalous charge collection from the substrate through the buried oxide. This substrate charge-collection mechanism can considerably increase the SEU-sensitive volume of SOI SRAMs, and must be included in single-event models if they are to provide accurate predictions of SOI device response in radiation environments.

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SEU-sensitive volumes in bulk and SOI SRAMs from first-principles calculations and experiments

Aluminum nitride (AlN) contour mode resonators have been of interest because of their high quality factor, low impedance, large number of frequencies on a single chip and compatibility with CMOS processes [1–3]. While AlN low insertion loss filters [1–3] and oscillators [4–7] have been demonstrated, CMOS integration has yet to be accomplished. This work represents the first time fully-released contour mode AlN microresonators have been integrated with CMOS circuitry to obtain completely monolithic frequency references.

Single-chip precision oscillators based on multi-frequency, high-Q aluminum nitride MEMS resonators

Focused ion microbeam and broadbeam heavy-ion experiments on capacitors and SRAMs are used to investigate increased saturation upset cross sections recently observed in some silicon-on-insulator (SOI) integrated circuits (ICs). Experiments performed on capacitors show a very strong bias and oxide thickness dependence for charge collection. In combination with three-dimensional (3-D) simulations, these data suggest that the mechanism for charge collection in capacitors is due to perturbation of the substrate electric fields by charge deposition in the substrate. For substrates biased in depletion, these perturbations induce displacement currents through the oxide. Charge collection by displacement currents can be substantially reduced or mitigated by using heavily doped substrates. Experiments performed on SRAMs also show enhanced charge collection from displacement currents. However, experimental data and 3-D simulations show that for SRAMs, a second mechanism also contributes to charge collection. The 3-D simulations suggest that the charge collection results from drain and body-tie heavy-ion strikes within a few tenths of a micron of the body-to-drain junctions. These charge collection mechanisms can substantially reduce the SEU hardness and soft-error reliability of commercial SOI ICs.

Charge collection in SOI capacitors and circuits and its effect on SEU hardness

The feasibility of developing an embeddable silicon-on-insulator (SOI) buried oxide MOS dosimeter (RadFET) has been demonstrated. This dosimeter takes advantage of the inherent properties for radiation-induced charge buildup in the buried oxides of commercial SOI wafers. Discrete SOI buried oxide RadFETs and fully-functional read-out circuitry have been fabricated in Sandia's CMOS7 radiation-hardened SOI technology. Discrete RadFETs have been irradiated under various radiation conditions and subjected to post-irradiation anneals. Data show only a small dose rate dependence and less than a 10% annealing or fade of the dosimeters output characteristics when irradiated with all pins shorted. These results show less fade than dual-dielectric RadFETs irradiated under the same bias conditions and support the use of SOI buried oxide RadFETs for low dose rate applications. Read-out circuitry has also been designed and fabricated to monitor changes in the ?off? state leakage current induced by radiation-induced charge buildup in the buried oxide dosimeter. The analog-to-digital output from the read-out circuit changes linearly with the ?off? state leakage current. Preliminary radiation characterizations of the read-out circuitry show no spurious effects of radiation-induced charge buildup in the read-out circuitry on the dosimeter output. These results indicate it is feasible to develop an embeddable SOI buried oxide RadFET as an attractive choice for many low power, low dose rate applications requiring real-time knowledge of total ionizing dose radiation levels.

An Embeddable SOI Radiation Sensor

Optical lithography (OL) is the manufacturing base for patterning of semiconductor integrated circuits (IC). Fundamental limits on optical imaging at features below 200-nm potentially limit its continued applicability. Interferometric lithography (IL) techniques provide a demonstrated, low-cost, large area nanoscale patterning capability with dense feature resolution to ∼ 50 nm. An important next step is demonstating the capability of applying IL to an existing pattern defined by OL. We report on a mix-and match scheme for writing a critical layer in an electrical linewidth test structure. Two important issues are the accuracy and the overlay of the grids for the two exposure techniques. Moire techniques are used to evaluate the grid absolute accuracy for IL with expanding spherical wavefronts. For a 1-m distance to the wafer plane, the period variation is less than 5×10 -5 over a 1 cm field leading to a placement error of±60 nm over the field. This error scales as the inverse square of the distance to the wafer plane and can be reduced to arbitrarily levels. Collimation will eliminate this systematic error to the extent that lens aberrations are compensated. Preliminary experimental results in qualitative agreement with the analysis are presented.

T.A. Hill

Papers

SEU-sensitive volumes in bulk and SOI SRAMs from first-principles calculations and experiments

Single-chip precision oscillators based on multi-frequency, high-Q aluminum nitride MEMS resonators

Charge collection in SOI capacitors and circuits and its effect on SEU hardness

An Embeddable SOI Radiation Sensor

Mix-and-match interferometric and optical lithographies for nanoscale structures