A simple yet effective total resistance slope-based method for extracting the effective channel mobility in deep submicrometer CMOS technology is developed. Using the slope of the measured total resistance versus mask length, the series resistance is removed from the measured total resistance, and mobility is extracted without involving the effective channel length. The new method facilitates mobility extraction in situations where the effective channel length is difficult to extract, such as in lightly-doped-drain (LDD) devices or at low temperatures. The new method also allows the series resistance to be any function of the gate bias, making the mobility extraction in LDD devices easier and more accurate.

A total resistance slope-based effective channel mobility extraction method for deep submicrometer CMOS technology

We present a new back junction approach for reducing SEU-induced charge collection in SiGe HBTS, and demonstrate its effectiveness in a state-of-the-art 200 GHz SiGe HBT using full 3-D device simulation. An additional n/sup +/ layer is used below the p-type isolation layer to form a back junction. The back junction limits potential funneling to within the p-type layer, which effectively limits the total amount of drift charge collection that is now shared by the collector-to-substrate junction and the back junction. The back junction also cuts off the diffusion charge coming from the substrate, further limiting charge collection by the HBT collector. A thinner p-type "substrate" layer and a better contact to the added n/sup +/ layer are shown to help reduce charge collection by the HBT collector, the sensitive node.

Simulation of a new back junction approach for reducing charge collection in 200 GHz SiGe HBTs

The drain current enhancement due to the velocity overshoot effects is found to be due to the electron velocity enhancement at the source end. Based on this observation, a new analytic model is proposed and verified by two-dimensional (2-D) simulations and experiments. From the results of the verifications, we conclude that our model predicts the drain current enhancement due to the velocity overshoot effects reasonably well. The effects of the device parameters, such as gate oxide thickness and channel doping concentration, on the drain current enhancement ran be readily found in our model.

Drain current enhancement due to velocity overshoot effects and its analytic modeling

A double quantum well Si/Si 1− x Ge x p-channel MOSFET (DQW-PMOS) is proposed and analyzed. Different Si/Si 1− x Ge x DQW designs both on bulk silicon and on silicon-on-insulator (SOI) substrates have been investigated using analytical and numerical approaches. Analytical modeling was used to investigate the threshold voltage of different channels. The numerical approach focused on the self-consistent 2D solution of the Schrodinger and Poisson equations to determine the confined hole density profile at different gate potentials. Both approaches reach the same conclusion regarding the best Si/Si 1− x Ge x DQW-PMOS design with respect to gate charge control and threshold voltage considerations. Among the investigated designs, the best hole confinement profile was for a structure with a 30%-Ge-content well at the substrate end (channel 1) and a 15%-Ge well close to the gate oxide (channel 2). Most of the confined holes in this structure are attributed to carriers from channel 1. For this design, the hole concentration profile in channel 1 was found to have a peak at the center of the channel. This retrograded DQW structure benefits from minimizing the mobility degradation due to interface scattering at the top Si/Si 1− x Ge x heterojunction. Therefore, the proposed structure of the DQW here shows that the built-in potential of the composite Si spacer layer and the top QW helps in the optimization of the hole distribution in the bottom QW. In addition, the above design offers better charge control compared to a structure with a 15%-Ge well at the substrate end and a 30%-Ge well close to the gate oxide. The implementation of the former structure leads to less 1/ f -noise and random telegraph signals. Hence, the structure is suitable for future analog applications.

Threshold voltage and charge control considerations in double quantum wellSi/Si1−xGex p-type MOSFETs

The metal-oxide-semiconductor (MOS) capacitors of Al2O3∕Ga2O3(Gd2O3) on n- and p-type In0.2Ga0.8As with different metal gates exhibited excellent capacitance-voltage (C-V) characteristics and remarkable thermodynamic stability after rapid thermal annealing up to 850°C. The flat-band voltage (Vfb), flat-band voltage shift (ΔVfb), threshold voltage (Vth), and frequency dispersion of the MOS capacitors with different metal gates were extracted from the C-V curves. The Vth values of Al2O3∕Ga2O3(Gd2O3)∕p-In0.2Ga0.8As were calculated to be about 0.04V (Al gate) and 1.15V (Ni gate) and those of Al2O3∕Ga2O3(Gd2O3)∕n-In0.2Ga0.8As −1.94V (Al gate) and −0.88V (Ni gate). The correlation between flat-band voltage and different metal gates indicates unpinned Fermi levels at the metal/dielectric interfaces.

Engineering of threshold voltages in molecular beam epitaxy-grown Al2O3∕Ga2O3(Gd2O3)∕In0.2Ga0.8As

A physical model of SiGe PMOS is presented. The condition for proper design ensuring the onset of strong inversion in the SiGe channel is modeled as a function of device structure. The threshold voltages and the inversion charge densities for both channels are also obtained. We show that the key to increasing the hole density in the SiGe channel lies in the reducing of the vertical electric field across the bottom Si/SiGe hetero-interface. Based on the modeling, a new bulk SiGe PMOS with a back pn junction sharing the depletion charge with the gate is proposed. Numerical simulation shows that the hole density in the SiGe channel of the back junction SiGe PMOS is comparable to that of the thin film SOI SiGe PMOS.

Inversion charge modeling of SiGe PMOS and approaches to increasing the hole density in the SiGe channel

A new definition of L eff which agrees well with electrical measurements using the channel resistance method is proposed, based on numerically simulated surface potential. Using the L eff definition, the physics underlying the fact that L eff can be considerably longer than the metallurgical channel length L eff is explored, and the independence of L eff on substrate bias V sub is clarified. The gate bias dependence of L eff in LDD MOSFET is clearly reflected by the proposed L eff definition.

Definition of effective channel length (Leff) in deep submicron MOSFETs based on numerically simulated surface potential

We propose here a back junction SiGe PMOS structure having a cross section of Poly/SiO 2 /Si-cap/SiGe/n-epi/p-substrate. The electrical coupling between the front gate and the back p-substrate/n-epi junction reduces the vertical field, thus improving the hole confinement and the SiGe channel mobility, resulting in an improved effective channel mobility. Numerical simulation shows that the back junction SiGe PMOS has a higher effective channel mobility compared to the fully-depleted SOI and conventional bulk SiGe PMOS.

https://ieeexplore.ieee.org/iel5/5435650/5435651/05435690.pdf

Back Junction SiGe PMOS - A New Structure with an Improved Effective Channel Mobility

A semi-empirical device model including velocity overshoot for subquartermicrometer MOSFET’s is presented, in which the velocity overshoot near source is attributed to the strong field here instead of the field gradient. Key features include successful modeling of the dependence of velocity overshoot on both channel length and doping, and closed form expressions for both drain current and transconductance. The proposed model is verified in comparison with experiments.

An Analytical Device Model Including Velocity Overshoot for Subquartermicrometer MOSFET

This paper describes the effect of substrate bias in bulk and SOI SiGe-channel p-MOSFETs. Applying a positive substrate bias to the bulk SiGe p-MOSFETs results in considerable shift of the SiGe channel threshold voltage towards more negative values, and considerable reduction of the saturated SiGe channel hole density, but has negligible effect on the surface channel threshold voltage and hole density. In SOI SiGe p-MOSFETs, the threshold voltages and hole densities are all negligibly affected by the negative substrate bias.

T.A. Tang

Papers

Inversion charge modeling of SiGe PMOS and approaches to increasing the hole density in the SiGe channel

Definition of effective channel length (Leff) in deep submicron MOSFETs based on numerically simulated surface potential

Back Junction SiGe PMOS - A New Structure with an Improved Effective Channel Mobility

An Analytical Device Model Including Velocity Overshoot for Subquartermicrometer MOSFET

Modeling of Substrate Bias Effect in Bulk and SOI SiGe-channel p-MOSFETs