In the recent past, there has been an evolution in wireless communications toward multifunctions and multistandard mobile terminals. Reducing the number of external components to a minimum is key when the same mobile terminal has to process several different standards. Highly integrated solutions in low-cost silicon technologies are thus required. Zero-IF and low-IF receiver architectures are most suitable for a high level of integration. This paper presents a review of global system for mobile communications, universal mobile telecommunication system, Bluetooth, and wireless local area network (IEEE802.11a, b, g and HiperLAN2) standards, likely to all be present in the "universal" terminal of the future, enabling global roaming and wireless connectivity. The various standards are analyzed in order to find the optimal architecture and the building-block specifications for the receive section, with particular care to the RF front-end. State-of-the-art solutions are discussed, with emphasis on direct conversion CMOS implementations. A multistandard architecture for a fully-integrated CMOS receiver is proposed.

Toward multistandard mobile terminals - fully integrated receivers requirements and architectures

Time jitter in continuous-time /spl Sigma//spl Delta/ modulators is a known limitation on the maximum achievable signal-to-noise-ratio (SNR). Analysis of time jitter in this type of converter shows that a switched-capacitor (SC) feedback digital-to-analog converter (DAC) reduces the sensitivity to time jitter significantly. In this paper, an I and Q continuous-time fifth-order /spl Sigma//spl Delta/ modulator with 1-bit quantizer and SC feedback DAC is presented, which demonstrates the improvement in maximum achievable SNR when using an SC instead of a switched-current (SI) feedback circuit. The modulator is designed for a GSM/CDMA2000/UMTS receiver and achieves a dynamic range of 92/83/72 dB in 200/1228/3840 kHz, respectively. The intermodulation distance IM2, 3 is better than 87 dB in all modes. Both the I and Q modulator consumes a power of 3.8/4.1/4.5 mW at 1.8 V. Processed in 0.18-/spl mu/m CMOS, the 0.55-mm/sup 2/ integrated circuit includes a phase-locked loop, two oscillators, and a bandgap.

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A triple-mode continuous-time /spl Sigma//spl Delta/ modulator with switched-capacitor feedback DAC for a GSM-EDGE/CDMA2000/UMTS receiver

An RF front-end for dual-band dual-mode operation is presented. The front-end consumes 22.5 mW from a 1.8-V supply and is designed to be used in a direct-conversion WCDMA and GSM receiver. The front-end has been fabricated in a 0.35-/spl mu/m BiCMOS process and, in both modes, can use the same devices in the signal path except the LNA input transistors. The front-end has a 27-dB gain control range, which is divided between the LNA and quadrature mixers. The measured double-sideband noise figure and voltage gain are 2.3 dB, 39.5 dB, for the GSM and 4.3 dB, 33 dB for the WCDMA, respectively. The linearity parameters IIP3 and IIP2 are -19 dBm, +35 dBm for the GSM and -14.5 dBm and +34 dBm for the WCDMA, respectively.

A dual-band RF front-end for WCDMA and GSM applications

This paper presents a novel approach to design a digitally programmable low pass filter (LPF) and variable gain amplifier (VGA) intended for a software-defined radio (SDR) front-end. These flexible analog circuits are driven by a network-on-chip (NoC) that is able to set performance parameters like cut-off frequency, selectivity, noise, and gain guaranteeing at any time a near-optimal power/perfomance trade-off. A design approach is proposed to tackle the challenges imposed by flexibility in analog design. A silicon prototype is realized in 0.13-μm CMOS technology with 1.2-V supply voltage to prove the validity of the proposed solution. The LPF provides a frequency tuning range between 0.35 MHz and 23.5 MHz with an adaptive integrated noise level between 85 μVrms and 163 μVrms whereby the power consumption conveniently varies from 0.72 mW to 21.6 mW according to the required performance. The VGA is made up of two cascaded gain stages and provides a gain range from about 0 dB to 39 dB with a reconfigurable power/bandwidth.

Flexible baseband analog circuits for software-defined radio front-ends

This paper presents a novel approach to design a digitally programmable low pass filter (LPF) and variable gain amplifier (VGA) intended for a software-defined radio (SDR) front-end. These flexible analog circuits are driven by a network-on-chip (NoC) that is able to set performance parameters like cut-off frequency, selectivity, noise, and gain guaranteeing at any time a near-optimal power/performance trade-off. A design approach is proposed to tackle the challenges imposed by flexibility in analog design. A silicon prototype is realized in 0.13-mum CMOS technology with 1.2-V supply voltage to prove the validity of the proposed solution. The LPF provides a frequency tuning range between 0.35 MHz and 23.5 MHz with an adaptive integrated noise level between 85 muVrms and 163 muVrms whereby the power consumption conveniently varies from 0.72 mW to 21.6 mW according to the required performance. The VGA is made up of two cascaded gain stages and provides a gain range from about 0 dB to 39 dB with a reconfigurable power/bandwidth.

Flexible Baseband Analog Circuits for Software-Defined Radio Front-Ends

A fifth-order analog CMOS RC-opamp baseband filter for a dual-mode cellular phone receiver was designed with maximum component sharing in the two modes, The filter meets the bandwidth specifications of both the PDC and WCDMA standards, which represent the two extremes with respect of the channel bandwidth. The total area of 4.8 mm/sup 2/ was minimized by reducing the filter order from five to three in the PDC mode, Also, the operational amplifiers with adjustable GBW were used to minimize PDC-mode power consumption. The capacitance matrices were made only partially overlapping to reduce the resistance spread, The largest resistors were implemented with T networks and the smallest capacitors with series connections to extend the range of feasible passive component values. The measured integrated input referred noise is 17 /spl mu/V and 47 /spl mu/V in the PDC and WCDMA modes, respectively. The IIP3 is +35 dBV in the WCDMA mode, and the circuit consumes 6.8 mW and 25.4 mW in the PDC and WCDMA modes, respectively. The supply voltage is 2.7 V.

A 2.7-V CMOS dual-mode baseband filter for PDC and WCDMA

A Dual-Mode 80MHz Bandpass DS-Modulator for a GSW/WCDMA IF-receiver

An 5th order analog CMOS RC-opamp baseband filter for a dual-mode cellular phone receiver was designed with maximum component sharing in the two modes. The filter meets the bandwidth specifications of both the PDC and WCDMA standards, which represent the two extremes in respect of the channel bandwith. The total area was minimized by reducing the filter order from five to three in the PDC-mode. Also, the operational amplifiers with adjustable GBW were used to minimize PDC-mode power consumption. The capacitance matrices were made only partially overlapping to reduce the resistance spread. The largest resistors were implemented with T networks and the smallest capacitors with series connections to extend the range of feasible passive component values. The measured frequency responses match the simulations very closely. The measured integrated input referred noise was 17 and 47uV in the PDC- and WCDMA-modes, respectively. The IIP3 was +35dBV in the WCDMA-mode and the circuit consumed 6.8mW and 25.4mW in the PDC- and WCDMA-modes, respectively.

A 2.7V CMOS dual-mode baseband filter for PDC and WCDMA

Direct tuning techniques of continuous-time filters for mobile radio receivers are discussed. Different design aspects are considered. A single-shot tuning is proposed especially for cases (CDMA) where sufficient time cannot be allocated for feedback based tuning as in time-division multiplexed radio systems (TDMA). A digital tuning circuit for the corner frequency of a continuous-time filter was designed and implemented. The chip was implemented using 0.35 µm CMOS technology. Because of the programmability the same circuit can be used to tune baseband filters in different mobile phone systems. Experimental results on GSM and WCDMA LP-filters are presented.

T. Hollman

Papers

A 2.7-V CMOS dual-mode baseband filter for PDC and WCDMA

A Dual-Mode 80MHz Bandpass DS-Modulator for a GSW/WCDMA IF-receiver

A 2.7V CMOS dual-mode baseband filter for PDC and WCDMA

Programmable direct digital tuning circuit for a continuous-time filter