Journal ArticleDOI
A 2.7-V CMOS dual-mode baseband filter for PDC and WCDMA
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TLDR
In this paper, a fifth-order analog CMOS RC-opamp baseband filter for a dual-mode cellular phone receiver was designed with maximum component sharing in the two modes, the filter meets the bandwidth specifications of both the PDC and WCDMA standards, which represent the two extremes with respect of the channel bandwidth.Abstract:
A fifth-order analog CMOS RC-opamp baseband filter for a dual-mode cellular phone receiver was designed with maximum component sharing in the two modes, The filter meets the bandwidth specifications of both the PDC and WCDMA standards, which represent the two extremes with respect of the channel bandwidth. The total area of 4.8 mm/sup 2/ was minimized by reducing the filter order from five to three in the PDC mode, Also, the operational amplifiers with adjustable GBW were used to minimize PDC-mode power consumption. The capacitance matrices were made only partially overlapping to reduce the resistance spread, The largest resistors were implemented with T networks and the smallest capacitors with series connections to extend the range of feasible passive component values. The measured integrated input referred noise is 17 /spl mu/V and 47 /spl mu/V in the PDC and WCDMA modes, respectively. The IIP3 is +35 dBV in the WCDMA mode, and the circuit consumes 6.8 mW and 25.4 mW in the PDC and WCDMA modes, respectively. The supply voltage is 2.7 V.read more
Citations
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Journal ArticleDOI
Toward multistandard mobile terminals - fully integrated receivers requirements and architectures
TL;DR: A multistandard architecture for a fully-integrated CMOS receiver is proposed, likely to all be present in the "universal" terminal of the future, enabling global roaming and wireless connectivity.
Journal ArticleDOI
A dual-band RF front-end for WCDMA and GSM applications
TL;DR: In this paper, an RF front-end for dual-band dual-mode operation is presented, which consumes 22.5 mW from a 1.8-V supply and is designed to be used in a direct-conversion WCDMA and GSM receiver.
Proceedings Article
Flexible baseband analog circuits for software-defined radio front-ends
TL;DR: A novel approach to design a digitally programmable low pass filter and variable gain amplifier intended for a software-defined radio (SDR) front-end that is able to set performance parameters like cut-off frequency, selectivity, noise, and gain guaranteeing at any time a near-optimal power/performance trade-off.
Journal ArticleDOI
Flexible Baseband Analog Circuits for Software-Defined Radio Front-Ends
TL;DR: In this article, the authors present an approach to design a digitally programmable low pass filter (LPF) and variable gain amplifier (VGA) intended for a software-defined radio (SDR) front-end.
Journal ArticleDOI
A 4th-order active-G/sub m/-RC reconfigurable (UMTS/WLAN) filter
TL;DR: A fourth-order low-pass continuous-time filter for a UMTS/WLAN receiver of a reconfigurable terminal is presented and the full chip has been designed using an automatic design tool, which is validated by the agreement between the experimental results and the expected performance.
References
More filters
Journal ArticleDOI
High-frequency CMOS continuous-time filters
H. Khorramabadi,Paul R. Gray +1 more
TL;DR: Fully integrated, high-frequency continuous-time filters can be realized in MOS technology using a frequency-locking approach to stabilize the time constants using a phase-locked loop.
Journal ArticleDOI
A cascaded sigma-delta pipeline A/D converter with 1.25 MHz signal bandwidth and 89 dB SNR
TL;DR: A low-noise multibit sigma-delta analog-to-digital converter (ADC) architecture suitable for operation at low oversampling ratios is presented, using an efficient high-resolution pipelined quantizer while avoiding loop stability degradation caused by pipeline latency.
Journal ArticleDOI
A 2-GHz wide-band direct conversion receiver for WCDMA applications
TL;DR: In this paper, a 2GHz direct conversion receiver for third-generation mobile communications using wideband code division multiple access achieves -114dBm sensitivity for 128-kb/s data at 4.096-Mcps spreading rate.
Journal ArticleDOI
Integrated continuous-time balanced filters for 16-b DSP interfaces
A.M. Durham,William Redman-White +1 more
TL;DR: In this article, a fully integrated, low-distortion, balanced, continuous-time filter fabricated in 5-V, 1.6-mu m CMOS is presented, where active RC structures are used in a leapfrog topology, with time constants set by integrated passive resistors and capacitors.
Journal ArticleDOI
A 3-V continuous-time filter with on-chip tuning for IS-95
TL;DR: In this paper, a low-voltage channel selection analog front end with continuous-time low-pass filters and on-chip tuning for a receiver in an IS-95 cellular phone is described.