Modern computer microprocessor chips are marvels of engineering complexity. For the current 45 nm technology node, there may be nearly a billion transistors on a chip barely 1 cm2 and more than 10 000 m of wiring connecting and powering these devices distributed over 9-10 wiring levels. This represents quite an advance from the first INTEL 4004B microprocessor chip introduced in 1971 with 10 μm minimum dimensions and 2 300 transistors on the chip! It has been disclosed that advanced microprocessor chips at the 32 nm node will have more than 2 billion transistors.1 For instance, Figure 1 shows a sectional 3D image of a 90 nm IBM microprocessor, containing several hundred million integrated devices and 10 levels of interconnect wiring, designated as the back-end-of-the-line (BEOL). Since the invention of microprocessors, the number of active devices on a chip has been exponentially increasing, approximately doubling every two years. This trend was first described in 1965 by Gordon Moore,2 although the original discussion suggested doubling the number of devices every year, and the phenomenon became popularly known as Moore’s Law. This progress has proven remarkably resilient and has persisted for more than 50 years. The enabler that has permitted these advances is known as scaling, that is, the reduction of minimum device dimensions by lithographic advances (photoresists, tooling, and process integration optimization) by ∼30% for each device generation.3 It allowed more active devices to be incorporated in a given area and improved the operating characteristics of the individual transistors. It should be emphasized that the earlier improvements in chip performance were achieved with very few changes in the materials used in the construction of the chips themselves. The increase of performance with scaling * Corresponding author. E-mail: gdubois@us.ibm.com. † IBM Almaden Research Center. ‡ Stanford University. Willi Volksen received his B.S. in Chemistry (magna cum laude) from New Mexico Institute of Mining and Technology in 1972 and his Ph.D. in Chemistry/Polymer Science from the University of Massachusetts, Lowell, in 1975. He then joined the research group of Prof. Harry Gray/Dr. Alan Rembaum at the California Institute of Technology as a postdoctoral fellow and upon completion of the one-year appointment joined Dr. Rembaum at the Jet Propulsion Laboratory as a Senior Chemist in 1976. In 1977 Dr. Volksen joined the IBM Research Division at the IBM Almaden Research Center in San Jose, CA, where he is an active research staff member in the Advanced Materials Group of the Science and Technology function.

Low dielectric constant materials.

Interlevel gaps between closely spaced circuit elements, such as closely spaced metal interconnect lines, are filed using a biased electron cyclotron resonance (ECR) deposition process. The gaps between circuit elements may be separated by distances of less than 0.6 microns and the gaps can have aspect rations in excess of 2.0. To fill such gaps between the circuit elements on a semiconductor wafer, the wafer is mounted in an ECR reaction chamber. A continuing flow of oxygen (O2) and silane (SiH4) gas is introduced into the ECR system's plasma and reaction chambers, respectively, while applying a microwave excitation so as to generate a plasma. High deposition rates and low film stress are achieved by controlling the flow of oxygen and silane so as to maintain an oxygen to silane gas flow ratio of less than 1.5. In addition, the wafer is cooled, typically using helium, so as to maintain wafer temperature below 300 degrees Celsius, because maintaining low temperatures during ECR deposition has been found to both increase the oxide deposition rate and to reduce the deposited film's compressive stress. This method makes it possible to achieve oxide deposition rates of 6000 Angstroms and above, with film stress below 1.5×109 dynes/cm2. Furthermore, these deposition rates and film stresses are obtained with a high degree of uniformity from wafer to wafer.

High throughput interlevel dielectric gap filling process

A method of depositing a dielectric film on a substrate in a process chamber of an inductively coupled plasma-enhanced chemical vapor deposition reactor. Gap filling between electrically conductive lines on a semiconductor substrate and depositing a cap layer are achieved. Films having significantly improved physical characteristics including reduced film stress are produced by heating the substrate holder on which the substrate is positioned in the process chamber.

Inductively coupled plasma cvd

A plasma processing system for plasma processing of substrates such as semiconductor wafers. The system includes a plasma processing chamber, a substrate support for supporting a substrate within the processing chamber, a dielectric member having an interior surface facing the substrate support, the dielectric member forming a wall of the processing chamber, a gas supply comprising one or more injector tubes extending rectilinearly in the plasma processing chamber and having one or more orifices in a sidewall for supplying gas into the chamber, and an RF energy source such as a planar coil which inductively couples RF energy through the dielectric member and into the chamber to energize the process gas into a plasma state. The gas is supplied through orifices located outside of regions at the distal tip of the injector tubes where electric field lines are concentrated. The arrangement minimizes clogging of the orifices since the orifices are located away from areas where most build-up of process byproducts occur on the injector tube.

Gas injection system for plasma processing

Low dielectric constant materials for interlayer dielectric

Silicon dioxide films were deposited on crystalline silicon substrates by electron cyclotron resonant (ECR) microwave plasma‐enhanced chemical vapor deposition (PECVD). Films were grown on Si〈100〉 substrates at temperatures of 140–600 °C, flow rates of 0.5–10 sccm SiH4, 10–30 sccm O2, and at a pressure of 10−3 Torr. Infrared absorption spectroscopy of the samples indicated no detectable SiH, OH, or SiOH groups. Neither an afterglow chemistry nor He dilution was required to eliminate H impurities as was previously reported for silicon oxide films deposited from rf plasmas. This suggests that significant differences exist between rf and ECR microwave plasma chemistries. We have found that the stoichiometry and index of refraction was not sensitive to oxidant ratio for a wide range of conditions in contrast to other studies. Stoichiometric SiO2 films, with good physical properties, were grown for a much wider range of oxidant ratios relative to those which are characteristic of the rf PECVD technique. In add...

Low‐temperature deposition of silicon dioxide films from electron cyclotron resonant microwave plasmas

Silicon dioxide films have been fabricated at growth temperatures ranging from 25 to 330 °C from an electron cyclotron resonant microwave plasma. Films were deposited from a SiH4/Ar/N2O reactant gas mixture. The minimum temperature required to fabricate high‐electrical‐quality silicon dioxide films is between 255 and 290 °C. In metal‐oxide‐semiconductor devices, electron injection field strengths and breakdown field strengths were as high as 5 and 8 MV/cm, respectively, for oxides grown above this temperature range. Films grown at temperatures slightly below the 255–290 °C range have much poorer electrical integrity. A concomitant increase in the refractive index was observed with the improvement in the electrical integrity of these films. The refractive index increased with increasing growth temperature and was in the range of 1.44–1.47. In the 255–290 °C temperature range, the refractive index of the silicon dioxide films reached approximately 1.46–1.47, and saturates thereafter. Infrared spectroscopy i...

Effects of substrate temperature on the electrical and physical properties of silicon dioxide films deposited from electron cyclotron resonant microwave plasmas

High-quality silicon dioxide films were deposited on a silicon substrate from an electron cyclotron resonant microwave plasma under the followiag conditions: substrate temperatures of 150 to 320'C, flow rates of 1.0 sccm of 10% SiH4 in Ar and 5.0 sccm of 02, 5 W (0.16 W/cm2) absorbed power, and at a pressure of 0.3 Pa. Films were determined to be stoichiometric, of high density, good bonding properties, and most importantly of excellent electrical integrity. A minimum deposition temperature required for good electrical properties appears to be about 285'C for the deposition conditions used in this study. Above this temperature the silicon dioxide films exhibited electrical strength characteristics similar to those found for thermally grown silicon dioxide films. More specifically, Fowler-Nordheim electron injection and destructive breakdown occurred at < 5 and 9 MV/cm, respectivcly, in metal-oxidesemiconductor devices for oxides deposited at 320'C. Films deposited under optimal conditions had IR spectra nearly identical to those of thermally grown silicon oxides and index of refraction of 1.456, as measured by ellipsometry. We conclude that using an ECR microwave plasma, Si02 films with physical and electronic properties comparable to thermally grown oxides can be deposited at low temperature (350'C) and low pressure (0.1 Pa).

Silicon dioxide films fabricated by electron cyclotron resonant microwave plasmas

Silicon dioxide films were deposited on crystalline silicon substrates by microwave plasma-enhanced CVD. An axial DC magnetic field in the plasma chamber produced electron cyclotron resonance (ECR) conditions at an excitation frequency of 2.45 GHz. Films were grown on Si

T. V. Herak

Papers

Low‐temperature deposition of silicon dioxide films from electron cyclotron resonant microwave plasmas

Effects of substrate temperature on the electrical and physical properties of silicon dioxide films deposited from electron cyclotron resonant microwave plasmas

Silicon dioxide films fabricated by electron cyclotron resonant microwave plasmas

Silicon dioxide films fabricated by ECR microwave plasmas